adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 40

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
TIMING SPECIFICATIONS
Timing specifications are detailed in this section.
Clock and Reset Timing
Table 22
Table 23
Table 22. Clock Input and Reset Timing
1
2
3
4
5
6
7
8
9
10
11
Parameter
Timing Requirements
t
t
t
t
t
t
t
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
Applies to PLL bypass mode and PLL nonbypass mode.
CLKIN frequency and duty cycle must not change on the fly.
If the DF bit in the PLL_CTL register is set, then the maximum t
Applies after power-up sequence is complete. At power-up, the processor’s internal phase locked loop requires no more than 2000 CLKIN cycles, while RESET is asserted,
Maximum value not specified due to variation resulting from boot mode selection and OTP memory programming.
Values specified assume no invalidation preboot settings in OTP page PBS00L. Invalidating a PBS set will increase the value by 1875 t
Applies only to boot modes BMODE=1,2,4,6,7,10,11,14,15.
Use default t
When enabled by OTP_RESETOUT_HWAIT bit. If regular HWAIT is not required in an application, the OTP_RESETOUT_HWAIT bit in the same page instructs the
Variances are mainly dominated by PLL programming instructions in PBS00L page and boot code differences between silicon revisions. The earlier is bypassed in boot mode
CKIN
CKINL
CKINH
BUFDLAY
WRST
RHWFT
RHWFT
assuming stable power supplies and CLKIN (not including startup time of external clock oscillator).
HWAIT or HWAITA to simulate Reset Output functionality. Then an external resistor is expected to pull the signal to the reset level, as the pin itself is in high-performance
mode during reset.
BMODE=0. Maximum value assumes PLL programming instructions do not cause the SCLK frequency to decrease.
and
and
SCLK
Figure 10
Figure 11
value unless PLL is reprogrammed during preboot. In case of PLL reprogramming use the new tSCLK value and add PLL_LOCKCNT settle time.
CLKIN Period
CLKIN Low Pulse
CLKIN High Pulse
CLKIN to CLKBUF Delay
RESET Asserted Pulsewidth Low
RESET High to First HWAIT/HWAITA Transition (Boot Host Wait Mode)
RESET High to First HWAIT/HWAITA Transition (Reset Output Mode)
CLKIN
CLKBUF
RESET
HWAIT(A)
describe Clock Input and Reset Timing.
describe Clock Out Timing.
1, 2, 3, 4
2
2
t
CKINL
t
CKIN
t
CKINH
5
Rev. A | Page 40 of 88 | October 2008
CKIN
Figure 10. Clock and Reset Timing
period is 50 ns.
t
WRST
VCO
t
t
BUFDLAY
RHWFT
, f
CCLK
7,10,11
, and f
6,7,8,9
SCLK
Min
20.0
8.0
8.0
11 t
6100 t
6100 t
settings discussed in
CKIN
CKIN
CKIN
+ 7900 t
t
BUFDLAY
CLKN
SCLK
Table 15
(typically).
Max
100.0
10
7000 t
and
Table 13 on Page
CKIN
Unit
ns
ns
ns
ns
ns
ns
ns
35.