adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 17

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

Sleep Operating Mode
The sleep mode reduces dynamic power dissipation by disabling
the clock to the processor core (CCLK). The PLL and system
clock (SCLK), however, continue to operate in this mode. Typi-
cally an external event or RTC activity will wake up the
processor. When in the sleep mode, assertion of a wakeup event
enabled in the SIC_IWRx register will cause the processor to
sense the value of the BYPASS bit in the PLL control register
(PLL_CTL). If BYPASS is disabled, the processor will transition
to the full on mode. If BYPASS is enabled, the processor will
transition to the active mode.
When in the sleep mode, system DMA access to L1 memory is
not supported.
Deep Sleep Operating Mode
Savings
The deep sleep mode maximizes dynamic power savings by dis-
abling the clocks to the processor core (CCLK) and to all
synchronous peripherals (SCLK). Asynchronous peripherals,
such as the RTC, may still be running but will not be able to
access internal resources or external memory. This powered-
down mode can only be exited by assertion of the reset interrupt
(RESET) or by an asynchronous interrupt generated by the
RTC. When in deep sleep mode, an asynchronous RTC inter-
rupt causes the processor to transition to the active mode.
Assertion of RESET while in deep sleep mode causes the proces-
sor to transition to the full on mode.
Hibernate State
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all
the synchronous peripherals (SCLK). The internal voltage regu-
lator for the processor can be shut off by using the
bfrom_SysControl() function in the on-chip ROM. This sets the
internal power supply voltage (V
greatest power savings mode. Any critical information stored
internally (memory contents, register contents, etc.) must be
written to a non-volatile storage device prior to removing power
if the processor state is to be preserved.
Since V
pins tri-state, unless otherwise specified. This allows other
devices that may be connected to the processor to have power
still applied without drawing unwanted current.
The internal supply regulator can be woken up by CAN, by the
MXVR, by the keypad, by the up/down counter, by the USB,
and by some GPIO pins. It can also be woken up by a real-time
clock wakeup event or by asserting the RESET pin. Waking up
from hibernate state initiates the hardware reset sequence.
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in hibernate
state. State variables may be held in external SRAM or DDR1
memory.
DDEXT
is still supplied in this mode, all of the external
−
Maximum Static Power Savings
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
−
High Dynamic Power Savings
−
DDINT
Maximum Dynamic Power
) to 0 V to provide the
Rev. A | Page 17 of 88 | October 2008
Power Domains
As shown in
port different power domains. The use of multiple power
domains maximizes flexibility while maintaining compliance
with industry standards and conventions. By isolating the inter-
nal logic of the ADSP-BF54x Blackfin processors into its own
power domain separate from the RTC and other I/O, the pro-
cessors can take advantage of dynamic power management
without affecting the RTC or other I/O devices. There are no
sequencing requirements for the various power domains.
Table 6. Power Domains
VOLTAGE REGULATION
The ADSP-BF54x Blackfin processors provide an on-chip volt-
age regulator that can generate processor core voltage levels
from an external supply (see specifications in
tions on Page
external components required to complete the power manage-
ment system. The regulator controls the internal logic voltage
levels and is programmable with the voltage regulator control
register (VR_CTL) in increments of 50 mV. This register can be
accessed using the bfrom_SysControl() function in the on-chip
ROM. To reduce standby power consumption, the internal volt-
age regulator can be programmed to remove power to the
processor core while keeping I/O power supplied. While in
hibernate state, V
still be applied, eliminating the need for external buffers. The
voltage regulator can be activated from this power down state by
assertion of the RESET pin, which will then initiate a boot
sequence. The regulator can also be disabled and bypassed at the
user’s discretion. For all automotive grade models, the internal
voltage regulator must not be used and V
V
age regulator circuit, see Switching Regulator Design
Considerations for the ASDP-BF533 Blackfin Processors (EE-
228).
Power Domain
All internal logic, except RTC, DDR1, and USB
RTC internal logic and crystal I/O
DDR1 external memory supply
USB internal logic and crystal I/O
Internal voltage regulator
MXVR PLL and logic
All other I/O
DDEXT
. For additional information regarding design of the volt-
Table
34).
DDEXT
Figure 6 on Page 18
6, the ADSP-BF54x Blackfin processors sup-
, V
DDRTC
, V
DDDDR
shows the typical
, V
DDVR
DDUSB
Operating Condi-
must be tied to
, and V
VDD Range
V
V
V
V
V
V
V
DDINT
DDRTC
DDDDR
DDUSB
DDVR
DDMP
DDEXT
DDVR
can