adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 19

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

All on-chip peripherals are clocked by the system clock (SCLK).
The system clock frequency is programmable by means of the
SSEL3–0 bits of the PLL_DIV register. The values programmed
into the SSEL fields define a divide ratio between the PLL output
(VCO) and the system clock. SCLK divider values are 1 through
15.
ratio is 4.
Table 7. Example System Clock Ratios
Note that the divisor ratio must be chosen to limit the system
clock frequency to its maximum of f
changed dynamically without any PLL lock latencies by writing
the appropriate values to the PLL divisor register (PLL_DIV)
using the bfrom_SysControl() function in the on-chip ROM.
The core clock (CCLK) frequency can also be dynamically
changed by means of the CSEL1–0 bits of the PLL_DIV register.
Supported CCLK divider ratios are 1, 2, 4, and 8, as shown in
Table
capability is useful for fast core frequency modifications.
Signal Name
SSEL3–0
0010
0110
1010
Table 7
CLKIN
8. The default ratio is 1. This programmable core clock
illustrates typical system clock ratios. The default
REQUIRES PLL SEQUENCING
DYNAMIC MODIFICATION
Figure 8. Frequency Modification Methods
0.5x - 64x
Divider Ratio
VCO/SCLK
2:1
6:1
10:1
PLL
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
SCLK
SCLK
VCO
Example Frequency Ratios
(MHz)
VCO
200
300
500
SCLK
133MHz
CCLK
DYNAMIC MODIFICATION
. The SSEL value can be
1, 2, 4, 8
1:15
ON-THE-FLY
SCLK
100
50
50
Rev. A | Page 19 of 88 | October 2008
CCLK
SCLK
The maximum CCLK frequency not only depends on the part’s
speed grade, it also depends on the applied V
Table 13
Table 8. Core Clock Ratios
BOOTING MODES
The ADSP-BF54x Blackfin processors have many mechanisms
(listed in
nal memory after a reset. The boot mode is defined by four
BMODE input pins dedicated to this purpose. There are two
categories of boot modes: master and slave. In master boot
modes, the processor actively loads data from parallel or serial
memories. In slave boot modes, the processor receives data
from an external host device.
Table 9. Booting Modes
The boot modes listed in
nisms for automatically loading the processor’s internal and
external memories after a reset. By default, all boot modes use
the slowest allowed configuration settings. Default settings can
be altered via the initialization code feature at boot time or by
proper OTP programming at pre-boot time. Some boot modes
require a boot host wait (HWAIT) signal, which is a GPIO out-
put signal that is driven and toggled by the boot kernel at boot
time. If pulled high through an external pull-up, the HWAIT
signal behaves active high and will be driven low when the pro-
Signal Name
CSEL1–0
00
01
10
11
BMODE3–0 Description
0000
0001
0010
0011
0100
0101
0110
0111
1000
1001
1010
1011
1100
1101
1110
1111
for details.
Table
Idle
Boot from 8- or 16-bit external flash memory
Boot from 16-bit asynchronous FIFO
Boot from serial SPI memory (EEPROM or flash)
Boot from SPI host device
Boot from serial TWI memory (EEPROM or flash)
Boot from TWI host
Boot from UART host
Reserved
Reserved
Boot from DDR1 SDRAM
Boot from OTP memory
Reserved
Boot from 8- or 16-bit NAND flash memory via NFC
Boot from 16-bit host DMA
Boot from 8-bit host DMA
9) for automatically loading internal and exter-
Divider Ratio
VCO/CCLK
1:1
2:1
4:1
8:1
−
no boot
Table 9
Example Frequency Ratios
(MHz)
VCO
300
300
500
200
provide a number of mecha-
DDINT
CCLK
300
150
125
25
voltage. See