adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 46

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
DDR1 SDRAM Read Cycle Timing
Table 28
Timing.
Cycle Timing.
Table 28. DDR1 SDRAM Read Cycle Timing, V
1
Parameter
Timing Requirements
t
t
t
t
t
t
Switching Characteristic
t
t
t
t
t
t
The t
AC
DQSCK
DQSQ
QH
RPRE
RPST
CK
CH
CL
AS
AH
OPW
1
CK
specification does not account for the effects of jitter.
Table 29
and
Figure 16
and
Access Window of DQ to CK
Access Window of DQS to CK
DQS-DQ Skew, DQS to Last DQ Valid
DQ-DQS Hold, DQS to First DQ to Go Invalid
DQS Read Preamble
DQS Read Postamble
Clock Period
Clock High Pulse Width
Clock low Pulse Width
Address and Control Output SETUP Time
Relative to CK
Address and Control Output HOLD Time
Relative to CK
Address and Control Output Pulse Width
Figure 17
describe DDR1 SDRAM Read Cycle
describe DDR1 SDRAM Write
DQ15-0
DQS
CK
Figure 16. DDR1 SDRAM Controller Read AC Timing
t DQSQ
t RPRE
DDDDR
t DQSCK (MAX)
Rev. A | Page 46 of 88 | October 2008
Nominal 2.6V
t QH
t AC (MAX)
t DQSQ
Min
–1.25
–1.25
t
1.00
1.00
2.20
t
0.9
0.4
7.50
0.45
0.45
t DQSCK (MIN)
CK
CK
/2 – 1.25 (for 7.50 ns
/2 – 1.75 (for t
t QH
t AC (MIN)
t RPST
CK
t CL
10 ns)
t CH
t
CK
< 10 ns)
Max
1.25
1.25
0.90
1.1
0.6
0.55
0.55
Unit
ns
ns
ns
ns
t
t
ns
t
t
ns
ns
ns
CK
CK
CK
CK