adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 22

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
For each of the boot modes, a 16-byte header is first read from
an external memory device. The header specifies the number of
bytes to be transferred and the memory destination address.
Multiple memory blocks may be loaded by any boot sequence.
Once all blocks are loaded, program execution commences from
the address stored in the EVT1 register.
Prior to booting, the pre-boot routine interrogates the OTP
memory. Individual boot modes can be customized or disabled
based on OTP programming. External hardware, especially
booting hosts, may monitor the HWAIT signal to determine
when the pre-boot has finished and the boot kernel starts the
boot process. However, the HWAIT signal does not toggle in
NAND boot mode. By programming OTP memory, the user
can instruct the preboot routine to also customize the PLL, volt-
age regulator, DDR1 controller, and/or asynchronous memory
interface controller.
The boot kernel differentiates between a regular hardware reset
and a wakeup-from-hibernate event to speed up booting in the
later case. Bits 6-4 in the system reset configuration (SYSCR)
register can be used to bypass the pre-boot routine and/or boot
kernel in case of a software reset. They can also be used to simu-
late a wakeup-from-hibernate boot in the software reset case.
The boot process can be further customized by “initialization
code.” This is a piece of code that is loaded and executed prior to
the regular application boot. Typically, this is used to configure
the DDR1 controller or to speed up booting by managing PLL,
clock frequencies, wait states, and/or serial bit rates.
The boot ROM also features C-callable function entries that can
be called by the user application at run-time. This enables sec-
ond-stage boot or booting management schemes to be
implemented with ease.
• Boot from 8-bit host DMA (BMODE=0xF)—In this mode,
returns using an RTS instruction. The routine may also be
the final application, which will never return to the boot
kernel.
the Host DMA port is configured in 8-bit interrupt mode
with little endian data format. Unlike other modes, the host
is responsible for interpreting the boot stream. It writes
data blocks individually to the Host DMA port. Before con-
figuring the DMA settings for each block, the host may
either poll the ALLOW_CONFIG bit in HOST_STATUS
or wait to be interrupted by the HWAIT signal. When
using HWAIT, the host must still check ALLOW_CONFIG
at least once before beginning to configure the Host DMA
Port. The host will receive an interrupt from the
HOST_ACK signal every time it is allowed to send the next
FIFO depth’s worth (sixteen 32-bit words) of information.
When the host sends an HIRQ control command, the boot
kernel issues a CALL instruction to address 0xFFA0 0000.
It is the host's responsibility to ensure valid code has been
placed at this address. The routine at address 0xFFA0 0000
can be a simple initialization routine to configure internal
resources, such as the SDRAM controller, which then
returns using an RTS instruction. The routine may also be
the final application, which will never return to the boot
kernel.
Rev. A | Page 22 of 88 | October 2008
INSTRUCTION SET DESCRIPTION
The Blackfin processor family assembly language instruction set
employs an algebraic syntax designed for ease of coding and
readability. The instructions have been specifically tuned to pro-
vide a flexible, densely encoded instruction set that compiles to
a very small final memory size. The instruction set also provides
fully featured multifunction instructions that allow the pro-
grammer to use many of the processor core resources in a single
instruction. Coupled with many features more often seen on
microcontrollers, this instruction set is very efficient when com-
piling C and C++ source code. In addition, the architecture
supports both user (algorithm/application code) and supervisor
(O/S kernel, device drivers, debuggers, ISRs) modes of opera-
tion, allowing multiple levels of access to core processor
resources.
The assembly language, which takes advantage of the proces-
sor’s unique architecture, offers the following advantages:
DEVELOPMENT TOOLS
The ADSP-BF54x Blackfin processors are supported with a
complete set of CROSSCORE® software and hardware develop-
ment tools, including Analog Devices emulators and
VisualDSP++® development environment. The same emulator
hardware that supports other Blackfin processors also fully
emulates the ADSP-BF54x Blackfin processors.
EZ-KIT Lite® Evaluation Board
For evaluation of ADSP-BF54x Blackfin processors, use the
ADSP-BF548 EZ-KIT Lite board available from Analog Devices.
Order part number ADZS-BF548-EZLITE. The board comes
with on-chip emulation capabilities and is equipped to enable
software development. Multiple daughter cards are available.
DESIGNING AN EMULATOR-COMPATIBLE
PROCESSOR BOARD
The Analog Devices family of emulators are tools that every sys-
tem developer needs to test and debug hardware and software
systems. Analog Devices has supplied an IEEE 1149.1 JTAG test
access port (TAP) on each JTAG processor. The emulator uses
• Seamlessly integrated DSP/MCU features are optimized for
• A multi-issue load/store modified-Harvard architecture,
• All registers, I/O, and memory are mapped into a unified
• Microcontroller features, such as arbitrary bit and bit-field
• Code density enhancements, which include intermixing of
both 8-bit and 16-bit operations.
which supports two 16-bit MAC or four 8-bit ALU + two
load/store + two pointer updates per cycle.
4G byte memory space, providing a simplified program-
ming model.
manipulation, insertion, and extraction; integer operations
on 8-, 16-, and 32-bit data-types; and separate user and
supervisor stack pointers.
16- and 32-bit instructions (no mode switching, no code
segregation). Frequently used instructions are encoded in
16 bits.