adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 23

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

the TAP to access the internal features of the processor, allow-
ing the developer to load code, set breakpoints, observe
variables, observe memory, and examine registers. The proces-
sor must be halted to send data and commands, but once an
operation has been completed by the emulator, the processor
system is set running at full speed with no impact on system
timing.
To use these emulators, the target board must include a header
that connects the processor’s JTAG port to the emulator.
For details on target board design issues including mechanical
layout, single processor connections, multiprocessor scan
chains, signal buffering, signal termination, and emulator pod
logic, see Analog Devices JTAG Emulation Technical Reference
(EE-68) on the Analog Devices web site under
www.analog.com/ee-notes. This document is updated regularly
to keep pace with improvements to emulator support.
MXVR BOARD LAYOUT GUIDELINES
MXVR Loop Filter RC network connected between the MLF_P
and MLF_M pins:
Capacitors:
Resistor:
The RC network should be located physically close to the
MLF_P and MLF_M pins on the board.
The RC network should be shielded using GND
Avoid routing other switching signals near the RC network to
avoid crosstalk.
MXI driven with external clock oscillator IC:
MXI/MXO with external crystal:
• C1: 0.047 μF (PPS type, 2% tolerance recommended)
• C2: 330 pF (PPS type, 2% tolerance recommended)
• R1: 330 Ω (1% tolerance)
• MXI should be driven with the clock output of a clock
• MXO should be left unconnected.
• Avoid routing other switching signals near the oscillator
• The crystal must be a fundamental mode crystal running at
• The crystal and load capacitors should be placed physically
• Board trace capacitance on each lead should not be more
• Trace capacitance plus load capacitance should equal the
• Avoid routing other switching signals near the crystal and
oscillator IC running at a frequency of 49.152 MHz or
45.1584 MHz.
and clock output trace to avoid crosstalk. When not possi-
ble, shield traces with ground.
a frequency of 49.152 MHz or 45.1584 MHz.
close to the MXI and MXO pins on the board.
than 3 pF.
load capacitance specification for the crystal.
components to avoid crosstalk. When not possible, shield
traces and components with ground.
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
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traces.
Rev. A | Page 23 of 88 | October 2008
V
Fiber optic transceiver (FOT) connections:
DDMP
• V
• A ferrite bead should be placed between the V
• Locally bypass V
• Avoid routing switching signals near to V
• The traces between the ADSP-BF549 processor and the
• The receive data trace connecting the FOT receive data
• The transmit data trace connecting the ADSP-BF549
• The receive data trace and the transmit data trace between
isolated power planes.
plane and the V
capacitors to GND
traces to avoid crosstalk.
FOT should be kept as short as possible.
output pin to the ADSP-BF549 PH6/MRX input pin should
have a 0 Ω series termination resistor placed close to the
FOT Receive Data output pin. Typically, the edge rate of
the FOT receive data signal driven by the FOT is very slow,
and further degradation of the edge rate is not desirable.
PH5/MTX output pin to the FOT transmit data input pin
should have a 27 Ω series termination resistor placed close
to the ADSP-BF549 PH5/MTX pin.
the ADSP-BF549 processor and the FOT should not be
routed close to each other in parallel over long distances to
avoid crosstalk.
/GND
DDMP
and GND
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—MXVR PLL power domain:
DDMP
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DDMP
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should be routed with wide traces or as
pin for noise isolation.
.
with 0.1 μF and 0.01 μF decoupling
DDMP
DDINT
and GND
power
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