adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 75

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
to be the difference between the ADSP-BF54x Blackfin proces-
sors’ output voltage and the input threshold for the device
requiring the hold time. A typical ΔV will be 0.4 V. C
bus capacitance (per data line), and I
three-state current (per data line). The hold time will be t
plus the minimum disable time (for example, t
chronous memory write cycle).
CAPACITIVE LOADING
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all balls (see
to V
Figure 53
time varies with capacitance. The delay and hold specifications
given should be derated by a factor derived from these figures.
The graphs in these figures may not be linear outside the ranges
shown.
DDEXT
(MEASURED)
(MEASURED)
t
DIS
V
V
/2 or V
OH
OL
through
OUTPUT STOPS DRIVING
DECAY
DDDDR
Figure 51. Output Enable/Disable
Figure 62 on Page 77
using the equation given above. Choose ΔV
REFERENCE
t
V
V
/2 depending on the pin under test.
DIS_MEASURED
OH
OL
SIGNAL
t
(MEASURED)
(MEASURED) +
DECAY
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
HIGH IMPEDANCE STATE
t
ENA
L
Figure
is the total leakage or
V
V
show how output rise
OUTPUT STARTS DRIVING
52). V
DDAT
t
1.75V
1.25V
ENA-MEASURED
LOAD
Rev. A | Page 75 of 88 | October 2008
t
for an asyn-
TRIP
L
(MEASURED)
is the total
(MEASURED)
is equal
V
OL
DECAY
V
OH
TYPICAL RISE AND FALL TIMES
V
Figure 53. Typical Rise and Fall Times (10% to 90%) vs. Load Capacitance for
LOAD
NOTES:
THE WORST-CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD), IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
4pF
14
12
10
8
6
4
2
0
0
Figure 52. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
50
70
50
400
2pF
50
Driver A at V
LOAD CAPACITANCE (pF)
45
0.5pF
TESTER PIN ELECTRONICS
100
RISE TIME
DDEXT
ZO = 50 (impedance)
TD = 4.04
= 2.25 V
150
T1
FALL TIME
1.18 ns
200
OUTPUT
DUT
250