adsp-bf548 Analog Devices, Inc., adsp-bf548 Datasheet - Page 71

• Manufacturer Part Number: adsp-bf548
• Description: Blackfin Embedded Processor
• Manufacturer: Analog Devices, Inc.

HOSTDP A/C Timing
Table 50
cycle timing requirements.
Table 50. Host Write Cycle Timing Requirements
1
Parameter
Timing Requirements
t
t
t
t
t
t
t
Switching Characteristics
t
t
NM (not measured)—This parameter is not measured because the time for which HOST_ACK is low is system design dependent.
SADWRL
HADWRH
WRWL
WRWH
DWRHRDY
HDATWH
SDATWH
DRDYWRL
RDYPWR
HOST_ADDR/HOST_CE Setup Before HOST_WR Falling Edge
HOST_ADDR/HOST_CE Hold After HOST_WR Rising Edge
HOST_WR Pulse Width Low (ACK Mode)
HOST_WR Pulse Width Low (INT Mode)
HOST_WR Pulse Width High or Time Between HOST_WR Rising Edge and
HOST_RD Falling Edge
HOST_WR Rising Edge Delay After HOST_ACK Rising Edge (ACK Mode)
Data Hold After HOST_WR Rising Edge
Data Setup Before HOST_WR Rising Edge
HOST_ACK Low Delay After HOST_WR/HOST_CE Asserted (ACK Mode)
HOST_ACK Low Pulse-Width for Write Access (ACK Mode)
and
Figure 39
−
describe the HOSTDP A/C host write
Host Write Cycle
ADSP-BF542/ADSP-BF544/ADSP-BF547/ADSP-BF548/ADSP-BF549
HOST_ADDR
HOST_D15-0
HOST_ACK
HOST_CE
HOST_WR
t
SADWRL
Rev. A | Page 71 of 88 | October 2008
Figure 39. HOSTDP A/C
t
DRDYWRL
t
SDATWH
t
t
RDYPWR
WRWL
−
Host Write Cycle
t
DWRHRDY
4
2.5
t
1.5 × t
2 × t
0
2.5
3.5
DRDYWRL
t
HADWRH
t
SCLK
WRWH
+ t
SCLK
RDYPRD
+ 8.7
Min
t
HDATWH
+ t
DWRHRDY
1.5 × t
NM
1
SCLK
Max
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns