MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 986
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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READI Module
24.6.2
The control and status information is accessed via the four auxiliary access public messages: device ready
for upload/download, upload request (tool requests information), download request (tool provides
information), and upload/download information (device/tool provides information).
To write control or status to memory-mapped locations the following sequence would be required.
24-18
1
1. The tool confirms that the device is ready (so as to not cancel an ongoing read write access). The
2. The tool waits for device ready for upload/download (TCODE 16) message before initiating next
RCPU
23:45
46:47
Bits
Data trace range start and end addresses must be word-aligned.
tool transmits the download request public message (TCODE 18) which contains write attributes,
write data, and target address.
access.
Accessing Memory-Mapped Locations Via
the Auxiliary Port
Nexus
Bits
24:2
1:0
There is no way to distinguish between off-core MPC500 special purpose
register (SPR) map and normal memory map accesses via the defined
address range control. If data trace ranges are set up such that the off-core
MPC500 SPR map falls within active ranges, then accesses to these off-core
MPC500 SPRs will be traced, and the messages will not be distinguishable
from accesses to normal memory map space. Off-core MPC500 SPRs
typically exist in the 8- to 16-Kbyte lowest memory block (0x2000 –
0x3FF0). If data or peripherals are mapped to this space, load/stores to
MPC500 SPRs will be indistinguishable from data or peripheral accesses.
Programmed Values
DTSA
Name
DTSA < DTEA
DTSA > DTEA
DTSA = DTEA
TA
Table 24-15. DTA 1 AND 2 Bit Descriptions (continued)
1
The Read/Write Start Field defines the starting address for the address range.
Refer to
The Read/Write Trace Field can be configured to allow enabling or disabling data read
and/or data write traces.
00 Disable data read and data write trace
x1 Enable data read trace
1x Enable data write trace
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 24-16. Data Trace Values
Table
24-16.
NOTE
DTSA
Range Selected
Word at DTSA
→
Invalid Range
Description
←
DTEA
Freescale Semiconductor
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