MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 802
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 802 of 1420
- Download datasheet (11Mb)
Modular Input/Output Subsystem (MIOS14)
17.12.6.2 MIOS14 Interrupt Level Register 1 (MIOS14LVL1)
This register contains the interrupt level that applies to the submodules number 15 to zero.
17.13 MIOS14 Function Examples
The versatility of the MIOS14 timer architecture is based on multiple counters and capture/compare
channel units interconnected on 16-bit counter buses. This section includes some typical application
examples to show how the submodules can be interconnected to form timing functions. The diagrams used
to illustrate these examples show only the blocks utilized for that function.
To illustrate the timing range of the MIOS14 in different applications, many of the following paragraphs
include time intervals quoted in microseconds and seconds. The assumptions used are that f
MHz with minimum overall prescaling (50 ns cycle) and with the maximum overall prescaling (32 µs
cycle). For other f
scale appropriately.
17.13.1 MIOS14 Input Double Edge Pulse Width Measurement
To measure the width of an input pulse, the MIOS14 double action submodule (MDASM) has two capture
registers so that only one interrupt is needed after the second edge. The software can read both edge
17-70
SRESET
10:15
10:15
Bits
Bits
0:4
5:7
8:9
0:4
5:7
8:9
Field
Addr
MSB
Name
Name
0
LVL
LVL
TM
TM
—
—
—
—
SYS
1
Figure 17-42. MIOS14 Interrupt Level Register 1 (MIOS14LVL1)
clock cycle rates and prescaler choices, the times mentioned in these paragraphs
Reserved
Interrupt request level. This field represents one of eight possible levels.
Time multiplexing. This field determines the multiplexed time slot
Reserved
Reserved
Interrupt request level. This field represents one of eight possible levels.
Time multiplexing. This field determines the multiplexed time slot.
Reserved
—
2
3
Table 17-42. MIOS14LVL0 Bit Descriptions
Table 17-43. MIOS14LVL1 Bit Descriptions
MPC561/MPC563 Reference Manual, Rev. 1.2
4
5
LVL
0000_0000_0000_0000
6
0x30 6C70
7
Description
Description
8
TM
9
10
11
12
—
Freescale Semiconductor
13
SYS
14
is at 40
LSB
15
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