MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 172
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Central Processing Unit
Integer instructions operate on byte, half-word, and word operands. Floating-point instructions operate on
single-precision (one word) and double-precision (one double word) floating-point operands. The
PowerPC ISA architecture uses instructions that are four bytes long and word-aligned. It provides for byte,
half-word, and word operand loads and stores between memory and a set of 32 GPRs.
Computational instructions do not modify memory. To use a memory operand in a computation and then
modify the same or another memory location, the memory contents must be loaded into a register,
modified, and then written back to the target location with distinct instructions.
PowerPC ISA-compliant processors follow the program flow when they are in the normal execution state.
However, the flow of instructions can be interrupted directly by the execution of an instruction or by an
asynchronous event. Either kind of exception may cause one of several components of the system software
to be invoked.
3.10.1
Table 3-17
description of the instruction set.
3-28
add (add. addo addo.)
addc (addc. addco addco.)
adde (adde. addeo addeo.)
addi
addic
addic.
addis
addme (addme. addmeo addmeo.)
addze (addze. addzeo addzeo.)
and (and.)
andc (andc.)
andi.
andis.
b (ba bl bla)
— Synchronize
— Instruction synchronize
provides a summary of RCPU instructions. Refer to the RCPU Reference Manual for a detailed
Instruction Set Summary
This grouping of the instructions does not indicate which execution unit
executes a particular instruction or group of instructions.
Mnemonic
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 3-17. Instruction Set Summary
rD,rA,rB
rD,rA,rB
rD,rA,rB
rD,rA,SIMM
rD,rA,SIMM
rD,rA,SIMM
rD,rA,SIMM
rD,rA
rD,rA
rA,rS,rB
rA,rS,rB
rA,rS,UIMM
rA,rS,UIMM
target_addr
Operand Syntax
NOTE
Add
Add Carrying
Add Extended
Add Immediate
Add Immediate Carrying
Add Immediate Carrying and Record
Add Immediate Shifted
Add to Minus One Extended
Add to Zero Extended
AND
AND with Complement
AND Immediate
AND Immediate Shifted
Branch
Name
Freescale Semiconductor
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