MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 432
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Memory Controller
10.9.4
10-34
1,
Bits
30
31
1
It is recommended that this field hold values that are the power of 2 minus 1 (e.g., 2
HRESET
HRESET
Memory Controller Option Registers (OR0–OR3)
Field
Addr
Name
BI
V
MSB
AM
16
0
Burst inhibit
0 Memory controller drives BI negated (high). The bank supports burst accesses.
1 Memory controller drives BI asserted (low). The bank does not support burst accesses.
NOTE: Following a system reset, the BI bit is set.
Valid bit. When set, this bit indicates that the contents of the base-register and option-register
pair are valid. The CS signal does not assert until the V-bit is set.
NOTE: An access to a region that has no V-bit set may cause a bus monitor timeout. See
Table 10-9
Figure 10-24. Memory Controller Option Registers 1–3 (OR0–OR3)
17
1
Branch Register
0x2F C104 (OR0); 0x2F C10C (OR1); 0x2F C114 (OR2), 0x2F C11C (OR3)
Table 10-8. BR0–BR3 Bit Descriptions (continued)
ATM
18
2
BR0
BR1
BR2
BR3
for the reset value of this bit in BR0.
MPC561/MPC563 Reference Manual, Rev. 1.2
19
3
0000_0000
Table 10-9. BRx[V] Reset Value
CSNT
20
4
21
5
ACS
0000_0000_0000_0000
22
6
EHTR
23
7
Description
AM
1
24
8
BRx[V] Reset Value
25
ID20 & ID31
9
1111
SCY
ID3
10
26
0
0
11
27
3
- 1 = 7 [0b111]).
12
28
0
BSCY
Freescale Semiconductor
13
29
1
14
30
1
TRLX
LSB
15
31
0
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