MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 1324

• Manufacturer Part Number: MPC564EVB
• Description: KIT EVAL FOR MPC561/562/563/564
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC564EVB

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC56x
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MPC561, 562, 563, 564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

66-MHz Electrical Characteristics
G.10.2
PORESET or HRESET must be asserted during power-down prior to any supply dropping out of specified
operating conditions.
An additional constraint is placed on PORESET assertion since it is an asynchronous input. To assure that
the assertion of PORESET does not potentially cause stores to keep-alive RAM to be corrupted (store
single or store multiple) or non-coherent (store multiple), either of the following solutions is
recommended:
The amount of delay that should be added to PORESET assertion is dependent upon the frequency of
operation and the maximum number of store multiples executed that are required to be coherent. If store
multiples of more than 28 registers are needed and if the frequency of operation is lower that 66 MHz, the
delay added to PORESET assertion will need to be greater than 0.5 µs. In addition, if KAPWR features
are being used, PORESET should not be driven low while the V
G.11 AC Timing
Figure G-9
in
G-18
Figure G-10
•
•
Assert HRESET at least 0.5 µs prior to when PORESET is asserted.
Assert IRQ0 (non-maskable interrupt) at least 0.5 µs prior to when PORESET is asserted. The
service routine for IRQ0 should not perform any writes to keep-alive RAM.
displays generic examples of MPC561/MPC563 timing. Specific timing diagrams are shown
Keep-Alive RAM
through
Figure
G-35.
MPC561/MPC563 Reference Manual, Rev. 1.2
DDH
and V
DDL
supplies are off.
Freescale Semiconductor