MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 49
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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Freescale Semiconductor
Figure
Number
QSPI Status Register (SPSR)................................................................................................ 15-21
QSPI RAM............................................................................................................................ 15-23
CR[0:F] — Command RAM 0x30 51C0, 0x30 51DF.......................................................... 15-24
Flowchart of QSPI Initialization Operation.......................................................................... 15-28
Flowchart of QSPI Master Operation (Part 1) ...................................................................... 15-29
Flowchart of QSPI Master Operation (Part 2) ...................................................................... 15-30
Flowchart of QSPI Master Operation (Part 3) ...................................................................... 15-31
Flowchart of QSPI Slave Operation (Part 1) ........................................................................ 15-32
Flowchart of QSPI Slave Operation (Part 2) ........................................................................ 15-33
SCI Transmitter Block Diagram ........................................................................................... 15-43
SCI Receiver Block Diagram ............................................................................................... 15-44
SCCxR0 — SCI Control Register 0 ..................................................................................... 15-46
SCI Control Register 1 (SCCxR1)........................................................................................ 15-47
SCIx Status Register (SCxSR).............................................................................................. 15-49
SCI Data Register (SCxDR) ................................................................................................. 15-51
Start Search Example............................................................................................................ 15-57
QSCI1 Control Register (QSCI1CR).................................................................................... 15-60
QSCI1 Status Register (QSCI1SR)....................................................................................... 15-61
Queue Transmitter Block Enhancements ............................................................................. 15-63
Queue Transmit Flow ........................................................................................................... 15-66
Queue Transmit Software Flow ............................................................................................ 15-66
Queue Transmit Example for 17 Data Bytes ........................................................................ 15-67
Queue Transmit Example for 25 Data Frames ..................................................................... 15-69
Queue Receiver Block Enhancements .................................................................................. 15-70
Queue Receive Flow ............................................................................................................. 15-73
Queue Receive Software Flow ............................................................................................. 15-74
Queue Receive Example for 17 Data Bytes.......................................................................... 15-75
TouCAN Block Diagram ........................................................................................................ 16-1
Typical CAN Network............................................................................................................ 16-3
Extended ID Message Buffer Structure .................................................................................. 16-4
Standard ID Message Buffer Structure ................................................................................... 16-4
Relationship between System Clock and CAN Bit Segments ................................................ 16-9
CAN Controller State Diagram............................................................................................. 16-12
Interrupt Levels on IRQ with ILBS ...................................................................................... 16-21
TouCAN Message Buffer Memory Map .............................................................................. 16-24
TouCAN Module Configuration Register (CANMCR) ....................................................... 16-25
TouCAN Interrupt Configuration Register (CANICR) ........................................................ 16-27
Control Register 0 (CANCTRL0)......................................................................................... 16-27
Control Register 1 (CANCTRL1)......................................................................................... 16-28
Prescaler Divide Register...................................................................................................... 16-29
MPC561/MPC563 Reference Manual, Rev. 1.2
Figures
Title
Number
Page
xlix
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