MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 423
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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With dual mapping, aliasing of address spaces may occur. This happens when the region is dual-mapped
into a region which is also mapped into one of the four regions available in the memory controller. If code
or data is written to the dual-mapped region, care must be taken to avoid overwriting this code or data by
normal accesses of the chip-select region.
There is a match if:
Care must also be taken to avoid overwriting “normal” CSx data with dual-mapped code or data.
One way to avoid this situation is by disabling the chip-select region and enabling only the dual-mapped
region (DMBR[DME] = 1, but BRx[V] = 0).
Freescale Semiconductor
•
•
The attributes for the access are taken from one of the base and option registers of the appropriate
chip select
The chip-select region selected is determined by the CS line select bit field
“Dual-Mapping Base Register
where BA represents the bit field in the DMBR register.
bus_address[0:16] == {0000000,ISB[0:2],0,BA[1:6]}
MPC561/MPC563 Reference Manual, Rev. 1.2
(DMBR)”).
Figure 10-19
illustrates the phenomenon.
(Section 10.9.5,
Memory Controller
Eqn. 10-1
Eqn. 10-2
10-25
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