MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 564
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
- Current page: 564 of 1420
- Download datasheet (11Mb)
QADC64E Enhanced Mode Operation
14.3.8
The status registers contains information about the state of each queue and the current A/D conversion.
Except for the four flag bits (CF1, PF1, CF2, and PF2) and the two trigger overrun bits (TOR1 and TOR2),
all of the status register fields contain read-only data. The four flag bits and the two trigger overrun bits
are cleared by writing a zero to the bit after the bit was previously read as a one.
14-22
SRESET
Field CF1
Addr
Bits
0
Status Registers (QASR0 and QASR1)
MSB
0
Name
CF1
PF1
1
CF2
Queue 1 Completion Flag. CF1 indicates that a queue 1 scan has been completed. The
scan completion flag is set by the QADC64E when the input channel sample requested by
the last CCW in queue 1 is converted, and the result is stored in the result table.
The end-of-queue 1 is identified when execution is complete on the CCW in the location
prior to that pointed to by BQ2, when the current CCW contains an end-of-queue code
instead of a valid channel number, or when the currently completed CCW is in the last
location of the CCW RAM.
When CF1 is set and interrupts are enabled for that queue completion flag, the QADC64E
asserts an interrupt request at the level specified by IRL1 in the interrupt register
(QADCINT). The software reads the completion flag during an interrupt service routine to
identify the interrupt request. The interrupt request is cleared when the software writes a
zero to the completion flag bit, when the bit was previously read as a one. Once set, only
software or reset can clear CF1.
CF1 is maintained by the QADC64E regardless of whether the corresponding interrupt is
enabled. The software polls for CF1 bit to see if it is set. This allows the software to
recognize that the QADC64E is finished with a queue 1 scan. The software acknowledges
that it has detected the completion flag being set by writing a zero to the completion flag
after the bit was read as a one.
2
PF2 TOR1 TOR2
3
Figure 14-12. Status Register 0 (QASR0)
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 14-15. QASR0 Bit Descriptions
0x30 4810 (QASR0_A); 0x30 4C10 (QASR0_B)
4
5
0000_0000_0000_0000
6
7
Description
QS
8
9
10
11
12
CWP
Freescale Semiconductor
13
14
LSB
15
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