MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 370
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MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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External Bus Interface
The MPC561/MPC563 performs operand transfers through its 32-bit data port. If the transfer is controlled
by the internal memory controller, the MPC561/MPC563 can support 8- and 16-bit data port sizes.
The bus requires that the portion of the data bus used for a transfer to or from a particular port size be fixed.
A 32-bit port resides on DATA[0:31], a 16-bit port must reside on DATA[0:15], and an 8-bit port must
reside on DATA[0:7]. The MPC561/MPC563 always tries to transfer the maximum amount of data on all
bus cycles. For a word operation, it always assumes that the port is 32 bits wide when beginning the bus
cycle.
In
9-30
Figure
•
•
•
•
•
Word accesses require address bits 30 – 31 to equal zero
Burst accesses require address bits 30 – 31 to equal zero
OP0 is the most-significant byte of a word operand and OP3 is the least-significant byte.
The two bytes of a half-word operand are either OP0 (most-significant) and OP1 or OP2
(most-significant) and OP3, depending on the address of the access.
The single byte of a byte-length operand is OP0, OP1, OP2, or OP3, depending on the address of
the access.
9-22,
0
Figure
OP0
OP0
OP0
9-23,
Table
Figure 9-22. Internal Operand Representation
MPC561/MPC563 Reference Manual, Rev. 1.2
OP1
OP1
OP1
9-2, and
Table
OP2
OP2
OP2
9-3, the following conventions are used:
OP3
OP3
OP3
31
Word
Half-word
Byte
Freescale Semiconductor
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