MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 194

• Manufacturer Part Number: MPC564EVB
• Description: KIT EVAL FOR MPC561/562/563/564
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC564EVB

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC56x
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MPC561, 562, 563, 564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Central Processing Unit
3-50
1
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
If the exception occurs during an instruction fetch in Decompression On mode, the SRR0 register will contain a
compressed address.
Machine State Register (MSR)
Data/Storage Interrupt Status
Register (DSISR)
Register
Table 3-27. Register Settings for Alignment Exception
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
[16:31]
[12:13]
[15:16]
[18:21]
[22:26]
[27:31]
[0:15]
Other
[0:11]
Bits
ME
LE
14
17
IP
Set to the effective address of the instruction that caused the
exception.
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
No change
Set to value of ILE bit prior to the exception
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
For instructions that use register indirect with index addressing,
set to bits [29:30] of the instruction.
For instructions that use register indirect with immediate index
addressing, cleared.
set to bit 25 of the instruction.
For instructions that use register indirect with immediate index
addressing, set to bit 5 of the instruction.
For instructions that use register indirect with index addressing,
set to bits [21:24] of the instruction.
For instructions that use register indirect with immediate index
addressing, set to bits [1:4] of the instruction.
Set to bits [6:10] (source or destination) of the instruction.
Set to bits [11:15] of the instruction (rA). Set to either bits
[11:15] of the instruction or to any register number not in the
range of registers loaded by a valid form instruction, for lmw,
lswi, and lswx instructions. Otherwise undefined.
Cleared to 0
No change
Cleared to 0
Cleared to 0
Cleared to 0
For instructions that use register indirect with index addressing,
Loaded from bits [16:31] of MSR. In the current
Setting Description
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