MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 60
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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lx
Figure
Number
Synchronous Output Signals Timing ..................................................................................... G-26
Synchronous Active Pull-Up And Open Drain Outputs Signals Timing .............................. G-27
Synchronous Input Signals Timing........................................................................................ G-28
Input Data Timing In Normal Case ....................................................................................... G-29
External Bus Read Timing (GPCM Controlled – ACS = ‘00’)............................................. G-30
External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘10’)......................... G-31
External Bus Read Timing (GPCM Controlled – TRLX = ‘0’ ACS = ‘11’)......................... G-32
External Bus Read Timing (GPCM Controlled – TRLX = ‘1’, ACS = ‘10’, ACS = ‘11’)... G-33
Address Show Cycle Bus Timing .......................................................................................... G-34
Address and Data Show Cycle Bus Timing........................................................................... G-35
External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘0’) ...................... G-36
External Bus Write Timing (GPCM Controlled – TRLX = ‘0’, CSNT = ‘1’) ...................... G-37
External Bus Write Timing (GPCM Controlled – TRLX = ‘1’, CSNT = ‘1’) ...................... G-38
External Master Read From Internal Registers Timing......................................................... G-39
External Master Write To Internal Registers Timing ............................................................ G-40
Interrupt Detection Timing for External Edge Sensitive Lines ............................................. G-41
Debug Port Clock Input Timing ............................................................................................ G-42
Debug Port Timings............................................................................................................... G-42
Auxiliary Port Data Input Timing Diagram........................................................................... G-43
Auxiliary Port Data Output Timing Diagram ........................................................................ G-43
Enable Auxiliary From RSTI................................................................................................. G-44
Disable Auxiliary From RSTI................................................................................................ G-44
Reset Timing – Configuration from Data Bus....................................................................... G-45
Reset Timing – Data Bus Weak Drive During Configuration............................................... G-46
Reset Timing – Debug Port Configuration ............................................................................ G-47
JTAG Test Clock Input Timing ............................................................................................. G-48
JTAG Test Access Port Timing Diagram .............................................................................. G-48
Boundary Scan (JTAG) Timing Diagram.............................................................................. G-49
QSPI Timing – Master, CPHA = 0 ........................................................................................ G-54
QSPI Timing – Master, CPHA = 1 ........................................................................................ G-54
QSPI Timing – Slave, CPHA = 0 .......................................................................................... G-55
QSPI Timing – Slave, CPHA = 1 .......................................................................................... G-55
TPU3 Timing ......................................................................................................................... G-57
PPM_TCLK Timing .............................................................................................................. G-59
PPM Data Transfer Timing (SPI Mode)................................................................................ G-59
MCPSM Enable to VS_PCLK Pulse Timing Diagram ......................................................... G-60
MPWMSM Minimum Output Pulse Example Timing Diagram........................................... G-61
MCPSM Enable to MPWMO Output Pin Rising Edge Timing Diagram ............................. G-61
MPWMSM Enable To MPWMO Output Pin Rising Edge Timing Diagram ....................... G-62
MPWMSM Interrupt Flag to MPWMO Output Pin Falling Edge Timing Diagram............. G-62
MPC561/MPC563 Reference Manual, Rev. 1.2
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