MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 52
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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18-26
18-27
19-1
19-2
19-3
19-4
19-5
19-6
19-7
19-8
19-9
19-10
19-11
19-12
19-13
19-14
19-15
19-16
19-17
19-18
19-19
19-20
19-21
19-22
19-23
20-1
20-2
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20-5
20-6
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21-1
21-2
21-3
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21-8
lii
Figure
Number
Short Channels Register (SHORT_CH_REG) ..................................................................... 18-23
Scale Transmit Clock Register (SCALE_TCLK_REG)....................................................... 18-24
TPU3 Block Diagram ............................................................................................................. 19-1
TPU3 Interrupt Levels ............................................................................................................ 19-5
TCR1 Prescaler Control.......................................................................................................... 19-7
TCR2 Prescaler Control.......................................................................................................... 19-8
TPUMCR — TPU Module Configuration Register ............................................................. 19-11
DSCR — Development Support Control Register ............................................................... 19-12
DSSR — Development Support Status Register .................................................................. 19-14
TICR — TPU3 Interrupt Configuration Register ................................................................. 19-14
CIER — Channel Interrupt Enable Register......................................................................... 19-15
CFSR0 — Channel Function Select Register 0 .................................................................... 19-16
CFSR1 — Channel Function Select Register 1 .................................................................... 19-16
CFSR2 — Channel Function Select Register 2 .................................................................... 19-16
CFSR3 — Channel Function Select Register 3 .................................................................... 19-16
HSQR0 — Host Sequence Register 0................................................................................... 19-17
HSQR1 — Host Sequence Register 1................................................................................... 19-17
HSRR0 — Host Service Request Register 0 ........................................................................ 19-17
HSRR1 — Host Service Request Register 1 ........................................................................ 19-17
CPR0 — Channel Priority Register 0 ................................................................................... 19-18
CPR1 — Channel Priority Register 1 ................................................................................... 19-18
CISR — Channel Interrupt Status Register .......................................................................... 19-19
TPUMCR2 — TPU Module Configuration Register 2 ........................................................ 19-19
TPUMCR3 — TPU Module Configuration Register 3 ........................................................ 19-21
SIUTST — SIU Test Register .............................................................................................. 19-22
DPTRAM Configuration ........................................................................................................ 20-2
DPTRAM Memory Map......................................................................................................... 20-3
DPT Module Configuration Register (DPTMCR).................................................................. 20-3
RAM Array Base Address Register (RAMBAR)................................................................... 20-5
Multiple Input Signature Register High (MISRH) ................................................................. 20-5
Multiple Input Signature Register Low (MISRL) .................................................................. 20-6
MISC Counter (MISCNT) ...................................................................................................... 20-6
Block Diagram for a 512 Kbyte UC3F Module Configuration .............................................. 21-2
UC3F EEPROM Configuration Register (UC3FMCR) ......................................................... 21-5
UC3FMCRE— UC3F EEPROM Extended Configuration Register ..................................... 21-9
UC3F EEPROM High Voltage Control Register (UC3FCTL) ............................................ 21-11
PEGOOD Valid Time ........................................................................................................... 21-14
Shadow Information ............................................................................................................. 21-16
Hard Reset Configuration Word (UC3FCFIG) .................................................................... 21-16
512-Kbyte Array Configuration............................................................................................ 21-19
MPC561/MPC563 Reference Manual, Rev. 1.2
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