MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 56
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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24-73
24-74
24-75
24-76
24-77
24-78
24-79
24-80
24-81
24-82
24-83
24-84
24-85
24-86
24-87
24-88
24-89
25-1
25-2
25-3
25-4
25-5
A-1
A-2
A-3
A-4
A-5
A-6
A-7
A-8
A-9
A-10
A-11
A-12
A-13
A-14
C-1
C-2
C-3
C-4
lvi
Figure
Number
Error Message (Watchpoint Overrun) .................................................................................. 24-74
Ownership Trace Message Format ....................................................................................... 24-75
Error Message Format .......................................................................................................... 24-75
Ownership Trace Message.................................................................................................... 24-76
Error Message (Program/Data/Ownership Trace Overrun).................................................. 24-76
RCPU Development Access Multiplexing between READI and BDM Signals .................. 24-77
DSDI Message Format.......................................................................................................... 24-78
DSDO Message Format ........................................................................................................ 24-78
BDM Status Message Format ............................................................................................... 24-79
Error Message (Invalid Message) Format ............................................................................ 24-79
RCPU Development Access Flow Diagram ......................................................................... 24-81
RCPU Development Access Timing Diagram — Debug Mode Entry Out-of-Reset........... 24-83
Transmission Sequence of DSDx Data Messages ................................................................ 24-83
Error Message (Invalid Message) ......................................................................................... 24-85
DSDI Data Message (Assert Non-Maskable Breakpoint) .................................................... 24-85
DSDI Data Message (CPU Instruction — rfi) ...................................................................... 24-85
DSDO Data Message (CPU Data Out) ................................................................................. 24-86
Pin Requirement on JTAG...................................................................................................... 25-1
Test Logic Block Diagram...................................................................................................... 25-3
JTAG Mode Selection ............................................................................................................ 25-3
TAP Controller State Machine ............................................................................................... 25-4
Bypass Register..................................................................................................................... 25-31
Instruction Compression Alternatives ..................................................................................... A-3
Addressing Instructions with Compressed Address ................................................................ A-4
Compressed Target Address Generation by Direct Branches.................................................. A-5
Branch Right Segment Compression #1 .................................................................................. A-7
Branch Right Segment Compression #2 .................................................................................. A-8
Global Bypass Instruction Layout ........................................................................................... A-8
CLASS_1 Instruction Layout .................................................................................................. A-9
CLASS_2 Instruction Layout .................................................................................................. A-9
CLASS_3 Instruction Layout ................................................................................................ A-10
CLASS_4 Instruction Layout ................................................................................................ A-11
Code Compression Process.................................................................................................... A-12
Code Decompression Process ................................................................................................ A-13
I-Bus Support Control Register (ICTRL) .............................................................................. A-16
Decompressor Class Configuration Registers1 (DCCR
MPC561/MPC563 Power Distribution Diagram — 2.6 V .......................................................C-3
Power Distribution Diagram — 5 V and Analog .....................................................................C-3
Crystal Oscillator Circuit ..........................................................................................................C-4
RC Filter Example ....................................................................................................................C-5
MPC561/MPC563 Reference Manual, Rev. 1.2
Figures
Title
x
) ..................................................... A-19
Freescale Semiconductor
Number
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