MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 43
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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9-8
Freescale Semiconductor
Figure
Number
Periodic Interrupt Timer Count (PITC) .................................................................................. 6-45
Periodic Interrupt Timer Register (PITR)............................................................................... 6-45
SGPIO Data Register 1 (SGPIODT1) .................................................................................... 6-46
SGPIO Data Register 2 (SGPIODT2) .................................................................................... 6-47
SGPIO Control Register (SGPIOCR)..................................................................................... 6-48
Reset Status Register (RSR) ..................................................................................................... 7-5
Reset Configuration Basic Scheme........................................................................................... 7-8
Reset Configuration Sampling Scheme for
“Short” PORESET Assertion, Limp Mode Disabled ............................................................... 7-9
Reset Configuration Timing for “Short” PORESET Assertion, Limp Mode Enabled............. 7-9
Reset Configuration Timing for “Long” PORESET Assertion, Limp Mode Disabled.......... 7-10
Reset Configuration Sampling Timing Requirements............................................................ 7-10
Reset Configuration Word (RCW) ......................................................................................... 7-11
Clock Unit Block Diagram ....................................................................................................... 8-2
Main System Oscillator Crystal Configuration ........................................................................ 8-3
System PLL Block Diagram ..................................................................................................... 8-5
MPC561/MPC563 Clocks ........................................................................................................ 8-8
General System Clocks Select ................................................................................................ 8-11
Divided System Clocks Timing Diagram ............................................................................... 8-12
Clocks Timing For DFNH = 1 (or DFNL = 0) ....................................................................... 8-13
Clock Source Switching Flow Chart ...................................................................................... 8-15
Low-Power Modes Flow Diagram ......................................................................................... 8-20
IRAMSTBY Regulator Circuit ............................................................................................... 8-23
Basic Power Supply Configuration......................................................................................... 8-24
External Power Supply Scheme.............................................................................................. 8-25
Keep-Alive Register Key State Diagram................................................................................ 8-27
No Standby, No KAPWR, All System Power-On/Off ........................................................... 8-28
Standby and KAPWR, Other Power-On/Off .......................................................................... 8-29
System Clock and Reset Control Register (SCCR) ................................................................ 8-30
PLL, Low-Power, and Reset-Control Register (PLPRCR) .................................................... 8-34
Change of Lock Interrupt Register (COLIR).......................................................................... 8-36
IRAMSTBY Control Register (VSRMCR) ............................................................................ 8-37
Input Sample Window .............................................................................................................. 9-2
MPC561/MPC563 Bus Signals ................................................................................................ 9-3
Basic Transfer Protocol ............................................................................................................ 9-8
Basic Flow Diagram of a Single Beat Read Cycle ................................................................... 9-9
Single Beat Read Cycle – Basic Timing – Zero Wait States.................................................. 9-10
Single Beat Read Cycle – Basic Timing – One Wait State .................................................... 9-11
Basic Flow Diagram of a Single Beat Write Cycle ................................................................ 9-12
Single Beat Basic Write Cycle Timing – Zero Wait States .................................................... 9-13
MPC561/MPC563 Reference Manual, Rev. 1.2
Figures
Title
Number
Page
xliii
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