MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 591
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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The MCU system clock frequency (IMB3 system clock – f
QCLK is generated by a software selectable prescaler that divides f
conversion time to be maximized across f
waveform by setting the PRESCALER field in the QACR0 register.
When the value of PRESCALER > 0 the resulting frequency of QCLK is calculated using the following
formula:
The QADC64E requires that f
field is set to Zero, the resulting QCLK frequency is calculated to be:
Freescale Semiconductor
Prescaler Rate Selection
(from Control Register 0)
System Clock (F
Input Sample Time
(From CCW)
QUEUE 1 & 2 Timer
Mode Rate Selection
f
f
QCLK
QCLK
A change in the prescaler value while a conversion is in progress is likely to
corrupt the result from any conversion in progress. Therefore, any prescaler
write operation should be done only when both queues are in the disabled
modes.
= f
= f
SYSCLK
SYSCLK
SYS
)
Figure 14-23. QADC64E Clock Subsystem Functions
/ (PRESCALER + 1)
/ 2
SYSCLK
MPC561/MPC563 Reference Manual, Rev. 1.2
8
be at least twice f
SYSCLK
2 7
WARNING
2 8
. The software establishes the frequency of QCLK
2 9
2 10
Periodic / interval
Binary Counter
A/D Converter
State Machine
Timer Select
QCLK
2 11
2 12
SYSCLK
2 13
. Therefore if the value in the PRESCALER
2 14
( F
2 15
) is the basis of the QADC64E timing.
SYS
SYSCLK
2 16 2 17
QADC Clock
/ ÷2 to F
QADC CLOCK BLOCK
QADC64E Enhanced Mode Operation
thus allowing the A/D
Generate
Clock
SYS
2
/ ÷40 )
Periodic/interval
Trigger Event
for Q1 and Q2
SAR Control
SAR[9:0]
QCLK
14-49
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