MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 512

• Manufacturer Part Number: MPC564EVB
• Description: KIT EVAL FOR MPC561/562/563/564
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC564EVB

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC56x
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MPC561, 562, 563, 564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

QADC64E Legacy Mode Operation
To accommodate wide variations of the main MCU clock frequency (IMB3 clock — f
generated by a programmable prescaler which divides the MCU IMB3 clock to a frequency within the
specified QCLK tolerance range. To allow the A/D conversion time to be maximized across the spectrum
of IMB3 clock frequencies, the QADC64E prescaler permits the frequency of QCLK to be software
selectable. It also allows the duty cycle of the QCLK waveform to be programmable.
The software establishes the basic high phase of the QCLK waveform with the PSH (prescaler clock high
time) field in QACR0, and selects the basic low phase of QCLK with the prescaler clock low time (PSL)
field. The combination of the PSH and PSL parameters establishes the frequency of the QCLK.
13-48
Prescaler Rate Selection
(From Control Register 0):
Queue 1 & 2 Timer
Mode Rate Selection
IMB3 Clock
(F
High Time
Cycles (PSH)
Input Sample Time
from (CCW)
Low Time
Cycles (PSL)
SYS
)
A change in the prescaler value while a conversion is in progress is likely to
corrupt the result from any conversion in progress. Therefore, any prescaler
write operation should be done only when both queues are in the disabled
modes.
Figure 13-24. QADC64E Clock Subsystem Functions
5
Down Counter
8
One’s Complement
MPC561/MPC563 Reference Manual, Rev. 1.2
5-Bit
2
Compare
3
Detect
Zero
5
3
2 7
2 8
Load PSH
2 9
NOTE
2 10
PERIODIC/INTERVAL
Binary Counter
A/D Converter
State Machine
Timer Select
2 11
2 12
2 13
2 14
Reset QCLK
Set QCLK
2 15
2 16 2 17
(F
SYS
QADC64E Clock
/ 2 to F
Generate
Clock
10
2
SYS
//40 )
Freescale Semiconductor
SAR Control
SAR
SYS
Periodic / Interval
Trigger Event
for Q1 AND Q2
QCLK
), QCLK is