MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 203
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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See
When a data protection error exception is taken, instruction execution resumes at offset 0x1400 from the
base address indicated by MSR[IP].
3.15.4.16 Implementation-Dependent Debug Exceptions
Implementation-dependent debug exceptions occur in the following cases:
See
Freescale Semiconductor
1
•
•
•
Table 3-36
Table 3-37
Save/Restore Register 0 (SRR0)
Save/Restore Register 1 (SRR1)
If the exception occurs during a data access in Decompression On mode, the SRR0 register will contain the address
of the Load/Store instruction in compressed format.
Machine State Register (MSR)
Data Address Register (DAR)
Data/Storage Interrupt Status
When there is an internal breakpoint match (for more details, refer to
Support.”
When a peripheral breakpoint request is asserted to the RCPU.
When the development port request is asserted to the RCPU. Refer to
Support,” for details on how to generate the development port-interrupt request.
Register (DSISR)
Register Name
for data-protection-error exception register settings.
for debug-exception register settings.
Table 3-36. Register Settings Following a Data Protection Error Exception
1
MPC561/MPC563 Reference Manual, Rev. 1.2
DCMPEN
Other
Other
Bits
0:15
7:31
ME
0:3
LE
All
All
IP
4
5
6
Set to the effective address of the instruction that caused the
exception
implementation, bit 30 of the SRR1 is never cleared, except by
loading a zero value from MSR[RI]
No change
Bit is copied from ILE
This bit is set according to (BBCMCR[EN_COMP] AND
BBCMCR[EXC_COMP])
Cleared to 0
Set to 1 if the storage access is not permitted by the protection
mechanism. Otherwise cleared to 0
Cleared to 0
Set to 1 for a store operation and cleared to 0 for a load
operation
Cleared to 0
exception
Cleared to 0
Loaded from bits [16:31] of MSR. In the current
No change
Cleared to 0
Set to the effective address of the data access that caused the
Description
Chapter 23, “Development
Chapter 23, “Development
Central Processing Unit
3-59
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