MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 72
![KIT EVAL FOR MPC561/562/563/564](/photos/39/39/393946/mpc564evbimage_sml.jpg)
MPC564EVB
Manufacturer Part Number
MPC564EVB
Description
KIT EVAL FOR MPC561/562/563/564
Manufacturer
Freescale Semiconductor
Type
Microcontrollerr
Specifications of MPC564EVB
Contents
Module Board, Installation Guide, Power Supply, Cable, Software and more
Processor To Be Evaluated
MPC56x
Data Bus Width
32 bit
Interface Type
RS-232, Ethernet
For Use With/related Products
MPC561, 562, 563, 564
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
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21-7
21-8
21-9
21-10
22-1
22-2
22-3
22-4
22-5
22-6
22-7
23-1
23-2
23-3
23-4
23-5
23-6
23-7
23-8
23-9
23-10
23-11
23-12
23-13
23-14
23-15
23-16
23-17
23-18
23-19
23-20
23-21
23-22
23-23
23-24
23-25
23-26
23-27
23-28
Freescale Semiconductor
Table
Number
Program Interlock State Descriptions ................................................................................... 21-23
Erase Interlock State Descriptions ........................................................................................ 21-27
Censorship States .................................................................................................................. 21-30
Censorship Modes and Censorship Status ............................................................................ 21-31
Priorities of Overlay Regions ............................................................................................... 22-12
CALRAM Control Registers ................................................................................................ 22-13
CRAMMCR Bit Descriptions............................................................................................... 22-14
CRAMMCR Privilege Bit Assignment for 8-Kbyte Array Blocks ...................................... 22-15
CRAM_RBAx Bit Descriptions ........................................................................................... 22-16
RGN_SIZE Encoding ........................................................................................................... 22-16
CRAMOVLCR Bit Descriptions .......................................................................................... 22-17
VF Pins Instruction Encodings ............................................................................................... 23-3
VF Pins Queue Flush Encodings ............................................................................................ 23-3
VFLS Pin Encodings .............................................................................................................. 23-4
Detecting the Trace Buffer Start Point ................................................................................... 23-6
Fetch Show Cycles Control .................................................................................................... 23-7
Instruction Watchpoints Programming Options ................................................................... 23-15
Load/Store Data Events ........................................................................................................ 23-16
Load/Store Watchpoints Programming Options................................................................... 23-17
Check Stop State and Debug Mode ...................................................................................... 23-27
Trap Enable Data Shifted into Development Port Shift Register ......................................... 23-34
Debug Port Command Shifted Into Development Port Shift Register ................................. 23-34
Status / Data Shifted Out of Development Port Shift Register............................................. 23-35
Debug Instructions / Data Shifted into Development Port Shift Register ............................ 23-36
Development Support Programming Model......................................................................... 23-39
Development Support Registers Read Access Protection .................................................... 23-40
Development Support Registers Write Access Protection ................................................... 23-41
CMPA-CMPD Bit Descriptions ........................................................................................... 23-41
ECR Bit Descriptions............................................................................................................ 23-42
DER Bit Descriptions ........................................................................................................... 23-43
Breakpoint Counter A Value and Control Register (COUNTA).......................................... 23-45
CMPE–CMPF Bit Descriptions............................................................................................ 23-46
CMPG-CMPH Bit Descriptions ........................................................................................... 23-47
LCTRL1 Bit Descriptions..................................................................................................... 23-47
LCTRL2 Bit Descriptions..................................................................................................... 23-49
ICTRL Bit Descriptions........................................................................................................ 23-51
ISCT_SER Bit Descriptions ................................................................................................. 23-52
BAR Bit Descriptions ........................................................................................................... 23-53
Breakpoint Counter B Value and Control Register (COUNTB) ......................................... 23-46
MPC561/MPC563 Reference Manual, Rev. 1.2
Tables
Title
Number
Page
lxxii
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