MPC564EVB Freescale Semiconductor, MPC564EVB Datasheet - Page 561

• Manufacturer Part Number: MPC564EVB
• Description: KIT EVAL FOR MPC561/562/563/564
• Manufacturer: Freescale Semiconductor
• Type: Microcontrollerr

Specifications of MPC564EVB

• Contents: Module Board, Installation Guide, Power Supply, Cable, Software and more
• Processor To Be Evaluated: MPC56x
• Data Bus Width: 32 bit
• Interface Type: RS-232, Ethernet
• For Use With/related Products: MPC561, 562, 563, 564
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Freescale Semiconductor
Bits
3:7
0
1
2
8
RESUME
Name
SSE2
CIE2
PIE2
MQ2
of queue 2. The interrupt request is initiated when the conversion is complete for the CCW in
queue 2.
0 Disable the queue completion interrupt associated with queue 2
1 Enable an interrupt after the conversion of the sample requested by the last CCW in queue
the pause state. The interrupt request is initiated when conversion is complete for a CCW that
has the pause bit set.
0 Disable the pause interrupt associated with queue 2
1 Enable an interrupt after the conversion of the sample requested by a CCW in queue 2
Queue 2 Single-Scan Enable Bit. SSE2 enables a single-scan of queue 2 to start after a
trigger event occurs. The SSE2 bit may be set to a one during the same write cycle when the
MQ2 bits are set for one of the single-scan queue operating modes. The single-scan enable
bit can be written as a one or a zero, but is always read as a zero. The SSE2 bit enables a
trigger event to initiate queue execution for any single-scan operation on queue 2. The
QADC64E clears the SSE2 bit when the single-scan is complete. Refer to
more information.
0 Trigger events are not accepted for single-scan modes
1 Accept a trigger event to start queue 2 in a single-scan mode
Queue 2 Operating Mode. The MQ2 field selects the queue operating mode for queue 2.
Refer to
0 After suspension, begin executing with the first CCW in queue 2 or the current sub-queue
1 After suspension, begin executing with the aborted CCW in queue 2
Queue 2 Completion Software Interrupt Enable. CIE2 enables an interrupt upon completion
Queue 2 Pause Software Interrupt Enable. PIE2 enables an interrupt when queue 2 enters
2
which has the pause bit set
Table 14-14
MPC561/MPC563 Reference Manual, Rev. 1.2
Table 14-13. QACR2 Bit Descriptions
for more information.
Description
QADC64E Enhanced Mode Operation
Table 14-14
for
14-19