AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 983
![KIT EVAL FOR AT91SAM9G45](/photos/9/26/92642/at91sam9g45-ekes_sml.jpg)
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
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41.4.4.6
41.4.4.7
6438F–ATARM–21-Jun-10
Suspension of Transfers Between buffers
Ending Multi-buffer Transfers
b u f f e r s i s a f u n c t i o n o f D M A C _ C T R L A x . S R C _ D S C R , D M A C _ C F G x . S R C _ R E P ,
DMAC_CTRLAx.DST_DSCR and DMAC_CFGx.DST_REP registers.
At the end of every buffer transfer, an end of buffer interrupt is asserted if:
Note:
At the end of a chain of multiple buffers, an end of linked list interrupt is asserted if:
All multi-buffer transfers must end as shown in Row 1 of
every buffer transfer, the DMAC samples the row number, and if the DMAC is in Row 1 state,
then the previous buffer transferred was the last buffer and the DMAC transfer is terminated.
F o r r o w s 9 , 1 0 a n d 1 1 o f
DMAC_CTRLBx.AUTO is set), multi-buffer DMAC transfers continue until the automatic mode is
disabled by writing a ‘1’ in DMAC_CTRLBx.AUTO bit. This bit should be programmed to zero in
the end of buffer interrupt service routine that services the next-to-last buffer transfer. This puts
the DMAC into Row 1 state.
For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared) the user must setup the last buffer
d e s c r i p t o r i n m e m o r y s u c h t h a t b o t h L L I . D M A C _ C T R L B x . S R C _ D S C R a n d
LLI.DMAC_CTRLBx.DST_DSCR are one and LLI.DMAC_DSCRx is set to 0.
• the channel buffer interrupt is unmasked, DMAC_EBCIMR.BTC[n] = ‘1’, where n is the
• the channel end of chained buffer interrupt is unmasked, DMAC_EBCIMR.CBTC[n] = ‘1’,
channel number.
when n is the channel number.
The buffer complete interrupt is generated at the completion of the buffer transfer to the
destination.
T a b l e 4 1 - 2 o n p a g e 9 8 2
Table 41-2 on page
, ( D M A C _ D S C R x = 0 a n d
AT91SAM9G45
982. At the end of
983
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