AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 1105

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

45.6.2.6
6438F–ATARM–21-Jun-10
Dithering
Table 45-9.
The lookup table can be accessed by the host in R/W mode to allow the host to program and
check the values stored in the palette. It is mapped in the LCD controller configuration memory
map. The LUT is mapped as 16-bit half-words aligned at word boundaries, only word write
access is allowed (the 16 MSB of the bus are not used). For the detailed memory map, see
Table 45-16 on page
The lookup table contains 256 16-bit wide entries. The 256 entries are chosen by the program-
mer from the 2
For the structure of each LUT entry, see
Table 45-10. Lookup Table Structure in the Memory
In STN Monochrome, only the four most significant bits of the red value are used (16 gray
shades). In STN Color, only the four most significant bits of the blue, green and red value are
used (4096 colors).
In TFT mode, all the bits in the blue, green and red values are used. The LCDD unused bits are
tied to 0 when TFT palletized configurations are used (LCDD[18:16], LCDD[9:8], LCDD[2:0]).
The dithering block is used to generate the shades of gray or color when the LCD Controller is
used with an STN LCD Module. It uses a time-based dithering algorithm and Frame Rate Con-
trol method.
The Frame Rate Control varies the duty cycle for which a given pixel is turned on, giving the dis-
play an appearance of multiple shades. In order to reduce the flicker noise caused by turning on
and off adjacent pixels at the same time, a time-based dithering algorithm is used to vary the
pattern of adjacent pixels every frame. This algorithm is expressed in terms of Dithering Pattern
registers (DP_i) and considers not only the pixel gray level number, but also its horizontal
coordinate.
STN Mono
STN Color
STN Color
Address
00
01
...
FE
FF
DISTYPE
Red_value_0[4:0]
Red_value_1[4:0]
Red_value_254[4:0]
Red_value_255[4:0]
Palette Configurations (Continued)
16
possible combinations.
1125.
Configuration
PIXELSIZE
4
1, 2, 4, 8
16
Table
Green_value_0[5:0]
Green_value_1[5:0]
Green_value_254[5:0]
Green_value_255[5:0]
Data Output [15:0]
45-10.
Palette
Non-palletized
Palletized
Non-palletized
AT91SAM9G45
Blue_value_0[4:0]
Blue_value_1[4:0]
Blue_value_254[4:0]
Blue_value_255[4:0]
1105