AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 151
![KIT EVAL FOR AT91SAM9G45](/photos/9/26/92642/at91sam9g45-ekes_sml.jpg)
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
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19.7.6.3
Name:
Access:
Reset:
• EBI_CS1A: EBI Chip Select 1 Assignment
0 = EBI Chip Select 1 is assigned to the Static Memory Controller.
1 = EBI Chip Select 1 is assigned to the SDRAM Controller.
• EBI_CS3A: EBI Chip Select 3 Assignment
0 = EBI Chip Select 3 is only assigned to the Static Memory Controller and EBI_NCS3 behaves as defined by the SMC.
1 = EBI Chip Select 3 is assigned to the Static Memory Controller and the SmartMedia Logic is activated.
• EBI_CS4A: EBI Chip Select 4 Assignment
0 = EBI Chip Select 4 is only assigned to the Static Memory Controller and EBI_NCS4 behaves as defined by the SMC.
1 = EBI Chip Select 4 is assigned to the Static Memory Controller and the Compact Flash Logic Slot 0 is activated.
• EBI_CS5A: EBI Chip Select 5 Assignment
0 = EBI Chip Select 5 is only assigned to the Static Memory Controller and EBI_NCS5 behaves as defined by the SMC.
1 = EBI Chip Select 5 is assigned to the Static Memory Controller and the Compact Flash Logic Slot 1 is activated.
• EBI_DBPUC: EBI Data Bus Pull-Up Configuration
0 = EBI D0 - D15 Data Bus bits are internally pulled-up to the VDDIOM1 power supply.
1 = EBI D0 - D15 Data Bus bits are not internally pulled-up.
• EBI_DRIVE: EBI I/O Drive Configuration
This allows to avoid overshoots and give the best performances according to the bus load and external memories.
• DDR_DRIVE: DDR2 dedicated port I/O slew rate selection
This allows to avoid overshoots and give the best performances according to the bus load and external memories.
0 = Low Drive, optimized for load capacitance < 30 pF.
6438F–ATARM–21-Jun-10
Value
00
01
10
11
31
23
15
–
–
–
7
–
EBI Chip Select Assignment Register
optimized for 1.8V powered memories with Low Drive
optimized for 3.3V powered memories with Low Drive
optimized for 1.8V powered memories with High Drive
optimized for 3.3V powered memories with High Drive
30
22
14
CCFG_EBICSA
Read-write
0x0001_0000
–
–
–
6
–
Drive configuration
EBI_CS5A
29
21
13
–
–
–
5
EBI_CS4A
28
20
12
–
–
–
4
EBI_CS3A
Maximum load capacitance < 30 pF
Maximum load capacitance < 30 pF
Maximum load capacitance < 55 pF
Maximum load capacitance < 55 pF
27
19
11
–
–
–
3
DDR_DRIVE
26
18
10
–
–
2
–
Conditions
AT91SAM9G45
EBI_CS1A
25
17
–
9
–
1
EBI_DRIVE
EBI_DBPUC
24
16
–
8
0
–
151
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