AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 172
![KIT EVAL FOR AT91SAM9G45](/photos/9/26/92642/at91sam9g45-ekes_sml.jpg)
AT91SAM9G45-EKES
Manufacturer Part Number
AT91SAM9G45-EKES
Description
KIT EVAL FOR AT91SAM9G45
Manufacturer
Atmel
Series
AT91SAM Smart ARMr
Type
MCUr
Datasheets
1.AT91SAM9G45-EKES.pdf
(56 pages)
2.AT91SAM9G45-EKES.pdf
(1218 pages)
3.AT91SAM9G45-EKES.pdf
(66 pages)
Specifications of AT91SAM9G45-EKES
Contents
Board
Processor To Be Evaluated
SAM9G45
Data Bus Width
32 bit
Interface Type
I2C, SPI, UART
Maximum Operating Temperature
+ 50 C
Minimum Operating Temperature
- 10 C
Operating Supply Voltage
1.8 V to 3.3 V
For Use With/related Products
AT91SAM9G45
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
Q4626953
- Current page: 172 of 1218
- Download datasheet (19Mb)
20.2.7.7
Figure 20-8. NAND Flash Application Example
172
External Bus Interface
NAND Flash Signals
AT91SAM9G45
NAND Flash Support
External Bus Interfaces integrate circuitry that interfaces to NAND Flash devices.
The NAND Flash logic is driven by the Static Memory Controller on the NCS3 address space.
Programming the EBI_CS3A field in the EBI_CSA Register in the Chip Configuration User Inter-
face to the appropriate value enables the NAND Flash logic. For details on this register, refer to
the Bus Matrix Section. Access to an external NAND Flash device is then made by accessing
the address space reserved to NCS3 (i.e., between 0x4000 0000 and 0x4FFF FFFF).
The NAND Flash Logic drives the read and write command signals of the SMC on the NANDOE
and NANDWE signals when the NCS3 signal is active. NANDOE and NANDWE are invalidated
as soon as the transfer address fails to lie in the NCS3 address space. See
172
section.
The address latch enable and command latch enable signals on the NAND Flash device are
driven by address bits A22 and A21 of the EBI address bus. The command, address or data
words on the data bus of the NAND Flash device are distinguished by using their address within
the NCSx address space. The chip enable (CE) signal of the device and the ready/busy (R/B)
signals are connected to PIO lines. The CE signal then remains asserted even when NCSx is
not selected, preventing the device from returning to standby mode.
EBI
for more information. For details on these waveforms, refer to the Static Memory Controller
PIO
PIO
NCSx/NANDCS
D[7:0]
A[22:21]
NANDWE
NANDOE
Not Connected
CE
R/B
ALE
CLE
NOE
NWE
AD[7:0]
NAND Flash
Figure 20-8 on page
6438F–ATARM–21-Jun-10
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