AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 252

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

22.4.5
Figure 22-24. Trp and Trcd Timings
252
COMMAND
AT91SAM9G45
Multi-port Functionality
DQS[1:0]
SDCLK
BA[1:0]
DM1:0]
D[15:0]
A[12:0]
NOP
0
3
The SDRAM protocol imposes a check of timings prior to performing a read or a write access,
thus decreasing the performance of systems. An access to SDRAM is performed if banks and
rows are open (or active). To activate a row in a particular bank, it has to de-active the last open
row and open the new row. Two SDRAM commands must be performed to open a bank: Pre-
charge and Active command with respect to Trp timing. Before performing a read or write
command, Trcd timing must checked.
This operation represents a significative loss. (see
The multi-port controller has been designed to mask these timings and thus improve the band-
width of the system.
DDRSDRC is a multi-port controller since four masters can simultaneously reach the controller.
This feature improves the bandwidth of the system because it can detect four requests on the
AHB slave inputs and thus anticipate the commands that follow, PRECHARGE and ACTIVE
commands in bank X during current access in bank Y. This allows Trp and Trcd timings to be
masked (see
were already open. The best condition is met when the four masters work in different banks. In
the case of four simultaneous read accesses, when the four banks and associated rows are
open, the controller reads with a continuous flow and masks the cas latency for each different
access. To allow a continuous flow, the read command must be set at 2 or 3 cycles (cas latency)
before the end of current access. This requires that the scheme of arbitration changes since the
round-robin arbitration cannot be respected. If the controller anticipates a read access, and thus
before the end of current access a master with a high priority arises, then this master will not
serviced.
The arbitration mechanism reduces latency when conflicts occur, i.e., when two or more masters
try to access the SDRAM device at the same time.
PRCHG
NOP
Trp
4 cycles before performing a read command
Figure
ACT
22-25). In the best case, all accesses are done as if the banks and rows
NOP
Trcd
READ
BST
Latency =2
Figure
NOP
22-24).
Da Db
6438F–ATARM–21-Jun-10