AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 568

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

Figure 33-4. Fractional Baud Rate Generator
33.7.1.4
6438F–ATARM–21-Jun-10
SCK
Reserved
MCK/DIV
MCK
Baud Rate in Synchronous Mode or SPI Mode
USCLKS
0
1
2
3
clock divider. This feature is only available when using USART normal mode. The fractional
Baud Rate is calculated using the following formula:
The modified architecture is presented below:
If the USART is programmed to operate in synchronous mode, the selected clock is simply
divided by the field CD in US_BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided
directly by the signal on the USART SCK pin. No division is active. The value written in
US_BRGR has no effect. The external clock frequency must be at least 4.5 times lower than the
system clock. In synchronous mode master (USCLKS = 0 or 1, CLK0 set to 1), the receive part
limits the SCK maximum frequency to MCK/4.5,
When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the
value programmed in CD must be even if the user has to ensure a 50:50 mark/space ratio on the
SCK pin. If the internal clock MCK is selected, the Baud Rate Generator ensures a 50:50 duty
cycle on the SCK pin, even if the value programmed in CD is odd.
Baudrate
BaudRate
16-bit Counter
CD
=
---------------------------------------------------------------- -
8 2 Over
Modulus
=
Control
FP
SelectedClock
------------------------------------- -
SelectedClock
–
CD
CD
glitch-free
USCLKS = 3
+
FP
------ -
logic
FP
8
SYNC
0
CD
>1
1
0
1
0
OVER
Sampling
Divider
AT91SAM9G45
FIDI
0
1
SYNC
SCK
Baud Rate
Sampling
Clock
Clock
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