AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 980

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

41.4.3.3
41.4.4
41.4.4.1
41.4.4.2
6438F–ATARM–21-Jun-10
DMAC Transfer Types
Single Transactions
Multi-buffer Transfers
Buffer Chaining Using Linked Lists
Writing a 1 to the DMAC_SREQ[2x] register starts a source single transaction request, where x
is the channel number. Writing a 1 to the DMAC_SREQ[2x+1] register starts a destination single
transfer request, where x is the channel number.
Upon completion of the chunk transaction, the hardware clears the DMAC_SREQ[x] or
DMAC_SREQ[2x+1].
Software can poll the relevant channel bit in the DMAC_CREQ[2x]/DMAC_CREQ[2x+1] and
DMAC_SREQ[x]/DMAC_SREQ[2x+1] registers. When both are 0, then either the requested
chunk or single transaction has completed.
A DMAC transfer may consist of single or multi-buffers transfers. On successive buffers of a
multi-buffer transfer, the DMAC_SADDRx/DMAC_DADDRx registers in the DMAC are repro-
grammed using either of the following methods:
On successive buffers of a multi-buffer transfer, the DMAC_CTRLAx and DMAC_CTRLBx regis-
ters in the DMAC are re-programmed using either of the following methods:
When buffer chaining, using linked lists is the multi-buffer method of choice, and on successive
buffers, the DMAC_DSCRx register in the DMAC is re-programmed using the following method:
A buffer descriptor (LLI) consists of following registers, DMAC_SADDRx, DMAC_DADDRx,
DMAC_DSCRx, DMAC_CTRLAx, DMAC_CTRLBx.These registers, along with the
DMAC_CFGx register, are used by the DMAC to set up and describe the buffer transfer.
In this case, the DMAC re-programs the channel registers prior to the start of each buffer by
fetching the buffer descriptor for that buffer from system memory. This is known as an LLI
update.
DMAC buffer chaining is supported by using a Descriptor Pointer register (DMAC_DSCRx) that
stores the address in memory of the next buffer descriptor. Each buffer descriptor contains the
corresponding buffer descriptor (DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx,
DMAC_CTRLAx DMAC_CTRLBx).
To set up buffer chaining, a sequence of linked lists must be programmed in memory.
The DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx
registers are fetched from system memory on an LLI update. The updated content of the
DMAC_CTRLAx register is written back to memory on buffer completion.
981
chaining.
• Buffer chaining using linked lists
• Replay mode
• Contiguous address between buffers
• Buffer chaining using linked lists
• Replay mode
• Buffer chaining using linked lists
shows how to use chained linked lists in memory to define multi-buffer transfers using buffer
AT91SAM9G45
Figure 41-5 on page
980