AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 1174

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

46.14 DDRSDRC Timings
46.15 Peripheral Timings
46.15.1
46.15.1.1
1174
Master Write Mode
Master Read Mode
Slave Read Mode
Slave Write Mode
AT91SAM9G45
SPI
Maximum SPI Frequency
The DDRSDRC controller satisfies the timings of standard DDR2, LP-DDR, SDR and LP-SDR
modules.
DDR2, LP-DDR and SDR timings are specified by the JEDEC standard.
Supported speed grade limitations:
The following formulas give maximum SPI frequency in Master read and write modes and in
Slave read and write modes.
• DDR2-400 limited at 133MHz clock frequency (1.8V, 30pF on data/control, 10pF on CK/CK#)
• LP-DDR (1.8V, 30pF on data/control, 10pF on CK)
• SDR-100 (3.3V, 50pF on data/control, 10pF on CK)
• SDR-133 (3.3V, 50pF on data/control, 10pF on CK)
• LP-SDR-133 (1.8V, 30pF on data/control, 10pF on CK)
Tcyc = 5.0 ns, Fmax = 125 MHz
Tcyc = 6.0 ns, Fmax = 110 MHz
Tcyc = 7.5 ns, Fmax = 95 MHz
The SPI is only sending data to a slave device such as an LCD, for example. The limit is
given by SPI
speed (see
T
DataFlash (AT45DB642D), T
In the formula above, F
In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by
setup and hold timings SPI
the pad limit, the limit in slave read mode is given by SPCK pad.
For 3.3V I/O domain and SPI6, F
before sampling data.
f
f
SPCK
SPCK
valid
is the slave time response to output data after deleting an SPCK edge. For Atmel SPI
Max
Max
=
=
Section 46.9
2
--------------------------------------------------------
SPI
-------------------------------------------------------- -
SPI
(or SPI
0
6
orSPI
orSPI
5
) timing. Since it gives a maximum frequency above the maximum pad
SPCK
1
1
“I/Os”), the max SPI frequency is the one from the pad.
3
9
Max = 38.5 MHz @ VDDIO = 3.3V.
7
+
+
/SPI
valid
T
T
valid
setup
(orT
8
SPCK
(or SPI
v
Max = 33 MHz. T
) is 12 ns Max.
10
/SPI
11
). Since this gives a frequency well above
setup
is the setup time from the master
6438F–ATARM–21-Jun-10