AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 1201

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

Revision History
6438F–ATARM–21-Jun-10
Doc. Rev
6438F
Comments
Bus Matrix
- EBI_DRIVE and DDR_DRIVE bitfields edited in
- “12-layer” Matrix instead of “11-layer”
DDRSDRC
In
- TRTP bitfield reset value (0 --> 2) changed.
- 0 and 15’ cycles changed into ‘0 and 7’ in ”TRTP: Read to Precharge”.
- TXARD (-->2), TXARDS (-->6), and TRPA (-->0) reset values changed.
In
In
Electrical Characteristics
- Figure below
-
-
- Ultra low power Mode value changed in
-
Errata
-
-
-
-
- 3
parity”
External Memories
- DQM0-3 added to
-
-
-
- On
‘DDR2-LPDDR’ --> ‘DDRSDRC20’.
- All ‘DDR2SDRC’ changed into ‘DDRSDRC’.
Mechanical Characteristics
- New
- All ‘nominal’ changed into ‘typical’.
- An empty square after letter ‘V’ removed from the
PMC
- Note added to
Register”.
Section 46.14 “DDRSDRC Timings”
Table 46-17 “I/O Characteristics”
Section 46.15.1.1 “Maximum SPI Frequency”
“Boot ROM”
“Static Memory Controller (SMC)”
“Touch Screen (TSADCC)”
“USB High Speed Host Port (UHPHS) and Device Port (UDPHS)”
Table
Section 20.2.7.7 “NAND Flash Support”
Section 20. “External Memories”
Section 22.7.6 “DDRSDRC Timing 2 Parameter
Section 22.7.7 “DDRSDRC Low-power
Section 22.4.4.1 “Self Refresh
“Error Corrected Code Controller (ECC)”
Figure 6-1 “AT91SAM9G45 Memory
Figure 47-1 “324-ball TFBGA Package Drawing”
,
20-5, row ‘A15’ edited.
“Unsupported ECC per 512 words”
In the tables that follow, the most recent version appears first.
errata added.
Table 46-7, “Main Oscillator Characteristics”
Section 25.3 “Master Clock
Figure 20-4 “EBI Connections to Memory
errata added.
Mode”, UDP_EN bitfield replaced by UPD_MR.
reorganized.
and Notes below edited.
errata added.
updated.
Table 46-3, “Power Consumption for Different
edited.
Register”, UPD_MR bitfield added to the table at [21:20].
Mapping”, ‘DDR2-LPDDR-SDRAM’ --> ‘DDRSDRC1’ and
and
Controller”and
errata added:
added.
“Unsupported hardware ECC on 16-bit Nand Flash”
“EBI Chip Select Assignment Register”
Register”,
Section 49.1 “Marking”
and Max. weight changed in
“Uncomplete parity status when error in ECC
Section 25.11.12 “PMC Master Clock
edited.
Devices”.
errata added.
table.
Table 47-2
Modes”.
AT91SAM9G45
Change
Request
Ref.
6930
7171
7134
7146
7063
7134 -7193
6926
7195
7173
7148
6977
7165
7194
7192
7123
7027
6924
6946
6954
RFO
7106
1201