AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 297

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

24.6
24.6.1
24.6.2
24.6.3
6438F–ATARM–21-Jun-10
Main Oscillator
Main Oscillator Connections
Main Oscillator Startup Time
Main Oscillator Control
The Main Oscillator is designed for a 12 MHz fundamental crystal. The 12 MHz is an input of the
PLLA and the UPLL used to generate the 480 MHz USB High Speed Clock (UPLLCK).
Figure 24-4
Figure 24-4. Main Oscillator Block Diagram
The typical crystal connection is illustrated in
characteristics of the Main Oscillator, see the section “DC Characteristics” of the product
datasheet.
Figure 24-5. Typical Crystal Connection
The startup time of the 12 MHz Main Oscillator is given in the section “DC Characteristics” of the
product datasheet.
To minimize the power required to start up the system, the main oscillator is disabled after reset
and slow clock is selected.
The software enables or disables the main oscillator so as to reduce power consumption by
clearing the MOSCEN bit in the Main Oscillator Register (CKGR_MOR).
When disabling the main oscillator by clearing the MOSCEN bit in CKGR_MOR, the MOSCS bit
in PMC_SR is automatically cleared, indicating the main clock is off.
When enabling the main oscillator, the user must initiate the main oscillator counter with a value
corresponding to the startup time of the oscillator. This startup time depends on the crystal fre-
quency connected to the main oscillator.
shows the Main Oscillator block diagram.
XOUT
XIN
XIN
12M Main
PLLA and
Oscillator
XOUT
Divider
UPLL
Figure
24-5. For further details on the electrical
GND
Main Clock
MAINCK
UPLLCK
PLLA Clock
PLLACK
AT91SAM9G45
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