AT91SAM9G45-EKES Atmel, AT91SAM9G45-EKES Datasheet - Page 1132

• Manufacturer Part Number: AT91SAM9G45-EKES
• Description: KIT EVAL FOR AT91SAM9G45
• Manufacturer: Atmel
• Series: AT91SAM Smart ARMr
• Type: MCUr

Specifications of AT91SAM9G45-EKES

• Contents: Board
• Processor To Be Evaluated: SAM9G45
• Data Bus Width: 32 bit
• Interface Type: I2C, SPI, UART
• Maximum Operating Temperature: + 50 C
• Minimum Operating Temperature: - 10 C
• Operating Supply Voltage: 1.8 V to 3.3 V
• For Use With/related Products: AT91SAM9G45
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: Q4626953

45.12.9
Name: DMA2DCFG
Address:0x00500020
Access: Read-write
Reset value: 0x00000000
• ADDRINC: DMA 2D Addressing Address increment
When 2-D DMA addressing is enabled (bit DMA2DEN is set in register DMACON), this field specifies the number of bytes
that the DMA controller must jump between screen lines. Itb must be programmed as: [({address of first 32-bit word in a
screen line} - {address of last 32-bit word in previous line})]. In other words, it is equal to 4*[number of 32-bit words occu-
pied by each line in the complete frame buffer minus the number of 32-bit words occupied by each displayed line]. Bit
DMAUPDT in register DMACON must be written after writing any new value to this field in order to make the DMA control-
ler use this new value.
• PIXELOFF: DAM2D Addressing Pixel offset
When 2D DMA addressing is enabled (bit DMA2DEN is set in register DMACON), this field specifies the offset of the first
pixel in each line within the memory word that contains this pixel. The offset is specified in number of bits in the range 0-31,
so for example a value of 4 indicates that the first pixel in the screen starts at bit 4 of the 32-bit word pointed by register
DMABADDR1. Bits 0 to 3 of that word are not used. This example is valid for little endian memory organization. When
using big endian memory organization, this offset is considered from bit 31 downwards, or equivalently, a given value of
this field always selects the pixel in the same relative position within the word, independently of the memory ordering con-
figuration. Bit DMAUPDT in register DMACON must be written after writing any new value to this field in order to make the
DMA controller use this new value.
1132
31
23
15
–
–
7
AT91SAM9G45
LCD DMA 2D Addressing Register
30
22
14
–
–
6
29
21
13
–
–
5
28
20
12
–
4
ADDRINC
ADDRINC
27
19
11
–
3
PIXELOFF
26
18
10
–
2
25
17
–
9
1
6438F–ATARM–21-Jun-10
24
16
–
8
0