AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 92

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

The timing diagram below assumes the default pro-
gramming of ROMTMG (1001b = 9 CLK). After reading
the first byte, the PCnet-PCI II controller reads in three
more bytes by incrementing the lower portion of the
The host must program the Expansion ROM Base Ad-
dress register in the PCI configuration space before the
first access to the Expansion ROM. The PCnet-PCI II
controller will not react to any access to the Expansion
ROM until both MEMEN (PCI Command register, bit 1)
and ROMEN (PCI Expansion ROM Base Address regis-
ter, bit 0) are set to ONE. After the Expansion ROM is
enabled, the PCnet-PCI II controller will claim all mem-
ory read accesses with an address between ROMBASE
and ROMBASE + 64K – 4 (ROMBASE, PCI Expansion
ROM Base Address register, bits 31–11). The address
92
AMD
ERACLK
ERACLK
DEVSEL
DEVSEL
FRAME
FRAME
EROE
EROE
TRDY
STOP
TRDY
STOP
IRDY
IRDY
C/BE
C/BE
ERD
ERD
ERA
ERA
PAR
PAR
CLK
CLK
AD
AD
24 25 26 27 28 29 30
1
2
3
A[15:8]
4
Figure 40. Expansion ROM Bus Read Sequence
A[7:2],1,0
5
6
7
P R E L I M I N A R Y
31 32 33 34 35 36 37 38 39 40
8
Am79C970A
9
10
A[7:2],0,0
11 12 13 14 15 16 17 18 19 20
ROM address. After the last byte is strobed in, TRDY will
be asserted on clock 44. When the host tries to perform
a burst read of the Expansion ROM, the PCnet-PCI II
will disconnect the access at the second data phase.
output to the Expansion ROM is the offset from the ad-
dress on the PCI bus to ROMBASE. The PCnet-PCI II
controller aliases all accesses to the Expansion ROM of
the command types “Memory Read Multiple” and “Mem-
ory Read Line” to the basic Memory Read command.
Since setting MEMEN also enables memory mapped
access to the I/O resources, attention must be given to
the PCI Memory Mapped I/O Base Address register, be-
fore enabling access to the Expansion ROM. The host
must set the PCI Memory Mapped I/O Base Address
A[7:2],1,1
41 42 43
A[7:2],0,1
44 45
21 22
23
19436A-43