AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 114

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

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AMD
IDON
INTR
IENA
OWN bit in the last descriptor of a
transmit frame has been cleared
to indicate the frame has been
sent or an error occurred in
the transmission.
When TINT is set, INTA is as-
serted if IENA is ONE and the
mask bit TINTM (CSR3, bit 9)
is ZERO.
TINT will not be set if TINTOKD
(CSR122, bit 2) is set to ONE and
the transmission was successful.
Read/Write accessible always.
TINT is cleared by the host by
writing a ONE. Writing a ZERO
has no effect. TINT is cleared by
H_RESET, S_RESET or by set-
ting the STOP bit.
Initialization Done is set by the
PCnet-PCI II controller after the
initialization
completed. When IDON is set,
the PCnet-PCI II controller has
read
from memory.
When IDON is set, INTA is as-
serted if IENA is ONE and the
mask bit IDONM (CSR3, bit 8)
is ZERO.
Read/Write accessible always.
IDON is cleared by the host by
writing a ONE. Writing a ZERO
has no effect. IDON is cleared by
H_RESET, S_RESET or by set-
ting the STOP bit.
Interrupt Flag indicates that one
or more following interrupt caus-
ing conditions has occurred:
BABL, EXDINT, IDON, JAB,
MERR, MISS, MFCO, MPINT,
RVCC, RINT, SINT, SLPINT,
TINT, TXSTRT or UINT and the
associated mask or enable bit is
programmed to allow the event to
cause an interrupt. If IENA is set
to ONE and INTR is set, INTA will
be active. When INTR is set by
SINT or SLPINT, INTA will be ac-
tive independent of the state
of INEA.
Read accessible always. INTR is
read only. INTR is cleared by
clearing all of the active individ-
ual interrupt bits that have not
been masked out.
Interrupt Enable allows INTA to
be active if the Interrupt Flag is
set. If IENA is cleared to ZERO,
INTA will be disabled regardless
of the state of INTR.
the
initialization
sequence
P R E L I M I N A R Y
block
Am79C970A
has
5
4
3
2
RXON
TDMD
TXON
STOP
Read/Write accessible always.
IENA is set by writing a ONE and
cleared by writing a ZERO. IENA
is
S_RESET or by setting the
STOP bit.
Receive On indicates that the re-
ceive function is enabled. RXON
is set to ONE if DRX (CSR15, bit
0) is cleared to ZERO after the
START bit is set. If INIT and
START are set together, RXON
will not be set until after the in-
itialization
read in.
Read accessible always. RXON
is read only. RXON is cleared by
H_RESET, S_RESET or by set-
ting the STOP bit.
Transmit On indicates that the
transmit function is enabled.
TXON is set to ONE if DTX
(CSR15, bit 1) is cleared to
ZERO after the START bit is set.
If INIT and START are set to-
gether, TXON will not be set until
after the initialization block has
been read in.
Read accessible always. TXON
is read only. TXON is cleared by
H_RESET, S_RESET or by set-
ting the STOP bit.
Transmit Demand, when set,
causes the buffer management
unit to access the transmit de-
scriptor ring without waiting for
the poll-time counter to elapse. If
TXON is not enabled, TDMD bit
will be cleared and no transmit
descriptor ring access will occur.
If the DPOLL bit in CSR4 is set,
automatic polling is disabled and
TDMD can be used to start
a transmission.
Read/Write accessible always.
TDMD is set by writing a ONE.
Writing a ZERO has no effect.
TDMD will be cleared by the
buffer management unit when it
polls
TDMD is cleared by H_RESET,
S_RESET or by setting the
STOP bit.
STOP assertion disables the chip
from all DMA and network activ-
ity. The chip remains inactive
until either STRT or INIT are set.
If STOP, STRT and INIT are all
set together, STOP will override
STRT and INIT.
cleared
a
transmit
block
by
has
H_RESET,
descriptor.
been