AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 66

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

In applications that don’t use the PCI Latency Timer or
that don’t support preemption the following rules apply
to limit the time the PCnet-PCI II controller takes up on
the bus.
If DMAPLUS is cleared to ZERO, a maximum of 16
transfers will be performed by default. This default value
may be changed by writing to the DMA Transfer Counter
(CSR80). Note that DMAPLUS = 0 merely sets a maxi-
mum value. The minimum number of transfers in the bus
mastership period will be determined by all of the follow-
ing variables: the settings of the FIFO watermarks
(CSR80), the conditions of the FIFOs, the value of the
DMA Transfer Counter (CSR80) and the value of the
DMA Bus Activity Timer (CSR82).
If DMAPLUS is set to ONE, bursting will continue until
the transmit FIFO is filled to its high threshold (read
transfers) or the receive FIFO is emptied to its low
threshold (write transfers), or until the DMA Bus Activity
Timer (CSR82) has expired. The exact number of total
transfer cycles in the bus mastership period is
dependent on all of the following variables: the settings
of the FIFO watermarks, the conditions of the FIFOs, the
latency of the system bus to the PCnet-PCI II controller’s
bus request, and the speed of bus operation. The DMA
Transfer Counter is disabled when DMAPLUS is set to
ONE. The TRDY response time of the memory device
will also affect the number of transfers, since the speed
of the accesses will affect the state of the FIFO. During
accesses, the FIFO may be filling or emptying on the
network end. For example, on a receive operation, a
slower TRDY response will allow additional data to ac-
cumulate inside of the FIFO. If the accesses are slow
enough, a complete DWord may become available be-
fore the end of the bus mastership period and thereby
increase the number of transfers in that period. The gen-
eral rule is that the longer the Bus Grant latency, the
slower the bus transfer operations, the slower the clock
speed, the higher the transmit watermark or the lower
the receive watermark, the longer the total burst length
will be.
When a FIFO DMA burst operation is preempted, the
PCnet-PCI II controller will not relinquish bus ownership
until the PCI Latency Timer expires. The DMA Transfer
Counter will freeze at the current value while the
PCnet-PCI II controller is waiting to regain bus owner-
ship. It will continue counting when the FIFO DMA burst
operation restarts. The Bus Activity Timer will be reset to
its starting value when the PCnet-PCI II controller re-
gains bus ownership.
The PCI Latency Timer cannot be disabled. Systems
that support preemption and that want to control the
duration of the PCnet-PCI II controller bus mastership
period with the DMA Transfer Counter or the Bus
Activity Timer must program the PCI Latency Timer with
a high value so that it does not expire before the other
two registers do.
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AMD
P R E L I M I N A R Y
Am79C970A
BUFFER MANAGEMENT UNIT
The Buffer Management Unit (BMU) is a microcoded
state machine which implements the initialization proce-
dure and manages the descriptors and buffers. The
buffer management unit operates at half the speed of
the CLK input.
Initialization
PCnet-PCI II controller initialization includes the reading
of the initialization block in memory to obtain the operat-
ing parameters. The initialization block can be organ-
ized in two ways. When SSIZE32 (BCR20, bit 8) is at its
default value of ZERO, all initialization block entries are
logically 16-bits wide to be backwards compatible with
the Am79C90 C-LANCE and Am79C96x PCnet-ISA
family. When SSIZE32 (BCR20, bit 8) is set to ONE, all
initialization block entries are logically 32-bits wide.
Note that the PCnet-PCI II controller always performs
32-bit bus transfers to read the initialization block en-
tries. The initialization block is read when the INIT bit in
CSR0 is set. The INIT bit should be set before or concur-
rent with the STRT bit to insure correct operation. Once
the initialization block has been completely read in and
internal registers have been updated, IDON will be set in
CSR0, generating an interrupt (if IENA is set).
The PCnet-PCI II controller obtains the start address of
the initialization block from the contents of CSR1 (least
significant 16 bits of address) and CSR2 (most signifi-
cant 16 bits of address). The host must write CSR1 and
CSR2 before setting the INIT bit. The initialization block
contains the user defined conditions for PCnet-PCI II
controller operation, together with the base addresses
and length information of the transmit and receive
descriptor rings.
There is an alternate method to initialize the PCnet-PCI
II controller. Instead of initialization via the initialization
block in memory, data can be written directly into the ap-
propriate registers. Either method or a combination of
the two may be used at the discretion of the
programmer. Please refer to Appendix C for details on
this alternate method.
Re-Initialization
The transmitter and receiver sections of the PCnet-PCI
II controller can be turned on via the initialization block
(DTX, DRX, CSR15, bits 1–0). The states of the trans-
mitter and receiver are monitored by the host through
CSR0 (RXON, TXON bits). The PCnet-PCI II controller
should be re-initialized if the transmitter and/or the re-
ceiver were not turned on during the original initializa-
tion, and it was subsequently required to activate them
or if either section was shut off due to the detection of an
error condition (MERR, UFLO, TX BUFF error).
Re-initialization may be done via the initialization block
or by setting the STOP bit in CSR0, followed by writing