AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 162

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

A logical address is passed through the CRC generator,
producing a 32 bit result. The high order 6 bits of the
CRC is used to select one of the 64 bit positions in the
Logical Address Filter. If the selected filter bit is set,
the address is accepted and the frame is placed
into memory.
The Logical Address Filter is used in multicast address-
ing schemes. The acceptance of the incoming frame
based on the filter value indicates that the message may
be intended for the node. It is the node’s responsibility to
determine if the message is actually intended for the
node by comparing the destination address of the stored
message with a list of acceptable logical addresses.
If the Logical Address Filter is loaded with all ZEROs
and promiscuous mode is disabled, all incoming logical
addresses except broadcast will be rejected.
PADR
This 48-bit value represents the unique node address
assigned by the ISO 8802-3 (IEEE/ANSI 802.3) and
used for internal address comparison. PADR[0] is com-
pared with the first bit in the destination address of the
incoming frame. It must be ZERO since only the destina-
tion address of a unicast frames is compared to PADR.
The six hex-digit nomenclature used by the ISO 8802-3
(IEEE/ANSI 802.3) maps to the PCnet-PCI II controller
162
CRDA+0Ch
CRDA+00h
CRDA+04h
CRDA+08h
CRDA+0Ch
CRDA+00h
CRDA+04h
CRDA+08h
Address
Address
CRDA+00h
CRDA+02h
CRDA+04h
CRDA+06h
Address
AMD
OWN
OWN
31
31
OWN
15
ERR
1
0
ERR
30
30
FRAM
FRAM
29
29
ERR
14
1
0
Table 41. Receive Descriptor (SWSTYLE = 1,2)
Table 40. Receive Descriptor (SWSTYLE = 0)
Table 42. Receive Descriptor (SWSTYLE = 3)
OFLO
OFLO
28
28
FRAM
RCC
RCC
13
1
0
CRC
CRC
27
27
P R E L I M I N A R Y
OFLO
BUFF
BUFF
12
26
26
1
0
Am79C970A
RBADR[31:0]
STP
STP
25
25
CRC
RBADR[31:0]
RESERVED
RESERVED
11
RBADR[15:0]
PADR register as follows: the first byte is compared with
PADR[7:0], with PADR[0] being the least significant bit
of the byte. The second ISO 8802-3 (IEEE/ANSI 802.3)
byte is compared with PADR[15:8], again from the least
significant bit to the most significant bit, and so on. The
sixth byte is compared with PADR[47:40], the least sig-
nificant bit being PADR[40].
MODE
The mode register field of the initialization block is cop-
ied into CSR15 and interpreted according to the descrip-
tion of CSR15.
Receive Descriptors
When SWSTYLE (BCR20, bits 7–0) is set to ZERO,
then the software structures are defined to be 16
bits wide, and receive descriptors, (CRDA = Current
Receive Descriptor Address), are as shown in Table 40.
When SWSTYLE (BCR 20, bits 7–0) is set to ONE or
TWO, then the software structures are defined to be 32
bits wide, and receive descriptors, (CRDA = Current
Receive Descriptor Address), are as shown in Table 41.
When SWSTYLE (BCR 20, bits 7–0) is set to THREE,
then the software structures are defined to be 32 bits
wide, and receive descriptors, (CRDA = Current Re-
ceive Descriptor Address), are as shown in Table 42.
ENP
ENP
24
24
BUFF
BPE
BPE
23
23
10
PAM
PAM
22
22
STP
LAFM
9
LAFM
RPC
RPC
21
21
MCNT
BCNT
BAM
BAM
20
20
ENP
8
19–16
19–16
RES
RES
RBADR[23:16]
15–12
15–12
0000
1111
1111
0000
7–0
MCNT
MCNT
BCNT
BCNT
11–0
11–0