AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 123

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

CSR9: Logical Address Filter 1
Bit
31–16 RES
15–0LADRF[31:16]
CSR10: Logical Address Filter 2
Bit
31–16 RES
15–0LADRF[47:32]
CSR11: Logical Address Filter 3
Bit
31–16 RES
15–0LADRF[63:48]
Name
Name
Name
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Logical
LADRF[31:16]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on
this register.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Logical
LADRF[47:32]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on
this register.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Reserved locations. Written as
ZEROs and read as undefined.
Logical
LADRF[63:48]. The content of
this register is undefined until
loaded from the initialization
block after the INIT bit in CSR0
has been set or a direct register
write has been performed on
this register.
Description
Address
Address
Address
accessible
accessible
P R E L I M I N A R Y
Filter,
Filter,
Filter,
only
only
Am79C970A
CSR12: Physical Address Register 0
Bit
31–16 RES
15–0PADR[15:0]
CSR13: Physical Address Register 1
Bit
31–16 RES
15–0PADR[31:16]
CSR14: Physical Address Register 2
Bit
31–16 RES
15–0PADR[47:32]
Name
Name
Name
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Physical
PADR[15:0]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Physical
PADR[31:16]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Physical
PADR[47:32]. The content of this
register is undefined until loaded
from the initialization block after
the INIT bit in CSR0 has been set
or a direct register write has been
performed on this register.
Address
Address
Address
accessible
accessible
accessible
AMD
Register,
Register,
Register,
only
only
only
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