AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 113

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

13
12
CERR
MISS
PCnet-PCI II controller when the
transmitter has been on the
channel longer than the time
required to send the maximum
length frame. BABL will be
set if 1519 bytes or greater
are transmitted.
When BABL is set, INTA is as-
serted if IENA is ONE and the
mask bit BABLM (CSR3, bit 14)
is ZERO. BABL assertion will set
the ERR bit, regardless of the
settings of IENA and BABLM.
Read/Write accessible always.
BABL is cleared by the host by
writing a ONE. Writing a ZERO
has no effect. BABL is cleared by
H_RESET, S_RESET or by set-
ting the STOP bit.
Collision Error is set by the
PCnet-PCI II controller when the
device operates in half-duplex
mode and the collision inputs to
the AUI or to the GPSI port failed
to activate within 20 network bit
times after the chip terminated
transmission (SQE Test). This
feature is a transceiver test
feature. CERR reporting is dis-
abled when the AUI or GPSI in-
terface
PCnet-PCI II controller operates
in full-duplex mode.
In 10BASE-T mode, for both
half-duplex and full-duplex op-
eration, CERR will be set after a
transmission if the T-MAU is in
Link Fail state.
CERR assertion will not result in
an interrupt being generated.
CERR assertion will set the
ERR bit.
Read/Write accessible always.
CERR is cleared by the host by
writing a ONE. Writing a ZERO
has no effect. CERR is cleared
by H_RESET, S_RESET or by
setting the STOP bit.
Missed Frame is set by the
PCnet-PCI II controller when it
looses an incoming receive
frame because a receive descrip-
tor was not available. This bit is
the only immediate indication
that receive data has been lost
since there is no current receive
descriptor. The Missed Frame
Counter (CSR112) also incre-
ments each time a receive frame
is missed.
is
active
and
P R E L I M I N A R Y
Am79C970A
the
11
10
9
MERR
RINT
TINT
When MISS is set, INTA is as-
serted if IENA is ONE and the
mask bit MISSM (CSR3, bit 12) is
ZERO. MISS assertion will set
the ERR bit, regardless of the
settings of IENA and MISSM.
Read/Write accessible always.
MISS is cleared by the host by
writing a ONE. Writing a ZERO
has no effect. MISS is cleared by
H_RESET, S_RESET or by set-
ting the STOP bit.
Memory Error is set by the
PCnet-PCI II controller when it
requests the use of the system
interface bus by asserting REQ
and GNT has not been asserted
after a programmable length of
time. The length of time in
microseconds before MERR is
asserted will depend upon the
setting of the Bus Timeout regis-
ter (CSR100). The default setting
of CSR100 will set MERR after
153.6 s of bus latency.
When MERR is set, INTA is as-
serted if IENA is ONE and the
mask bit MERRM (CSR3, bit 11)
is ZERO. MERR assertion will
set the ERR bit, regardless of the
settings of IENA and MERRM.
Read/Write accessible always.
MERR is cleared by the host by
writing a ONE. Writing a ZERO
has no effect. MERR is cleared
by H_RESET, S_RESET or by
setting the STOP bit.
Receive Interrupt is set by the
PCnet-PCI II controller after the
last descriptor of a receive frame
has been updated by writing a
ZERO to the OWN bit. RINT may
also be set when the first descrip-
tor of a receive frame has been
updated by writing a ZERO to the
OWN bit if the LAPPEN bit of
CSR3 has been set to ONE.
When RINT is set, INTA is as-
serted if IENA is ONE and the
mask bit RINTM (CSR3, bit 10)
is ZERO.
Read/Write accessible always.
RINT is cleared by the host by
writing a ONE. Writing a ZERO
has no effect. RINT is cleared by
H_RESET, S_RESET or by
setting the STOP bit.
Transmit Interrupt is set by the
PCnet-PCI II controller after the
AMD
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