AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 67

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

to CSR15, and then setting the START bit in CSR0.
Note that this form of restart will not perform the same in
the PCnet-PCI II controller as in the CLANCE. In par-
ticular, upon restart, the PCnet-PCI II controller reloads
the transmit and receive descriptor pointers with their
respective base addresses. This means that the soft-
ware must clear the descriptor OWN bits and reset its
descriptor ring pointers before restarting the PCnet-PCI
II controller. The reload of descriptor base addresses is
performed in the CLANCE only after initialization, so a
restart of the CLANCE without initialization leaves the
CLANCE pointing at the same descriptor locations as
before the restart.
Suspend
The PCnet-PCI II controller offers a suspend mode that
allows easy updating of the CSR registers without going
through a full re-initialization of the device. The suspend
mode also allows stopping the device with orderly termi-
nation of all network activity.
The host requests the PCnet-PCI II controller to
enter the suspend mode by setting SPND (CSR5, bit 0)
to ONE. When the host sets SPND to ONE, the
PCnet-PCI II controller first finishes all on-going trans-
mit activity and updates the corresponding transmit de-
scriptor entries. It then finishes all on-going receive
activity and updates the corresponding receive descrip-
tor entries. It then sets the read-version of SPND to ONE
and enters the suspend mode. The host must poll SPND
until it reads back ONE to determine that the PCnet-PCI
II controller has entered the suspend mode. In suspend
mode, all of the CSR and BCR registers are accessible.
As long as the PCnet-PCI II controller is not reset while
in suspend mode (by H_RESET, S_RESET or by set-
ting the STOP bit), no re-initialization of the device is re-
quired after the device comes out of suspend mode.
When the host clears SPND, the PCnet-PCI II controller
will leave the suspend mode and will continue at the
transmit and receive descriptor ring locations, where it
had left off.
Buffer Management
Buffer management is accomplished through message
descriptor entries organized as ring structures in
memory. There are two descriptor rings, one for
transmit and one for receive. Each descriptor describes
a single buffer. A frame may occupy one or more buff-
ers. If multiple buffers are used, this is referred to as
buffer chaining.
Descriptor Rings
Each descriptor ring must occupy a contiguous area of
memory. During initialization the user-defined base ad-
dress for the transmit and receive descriptor rings, as
well as the number of entries contained in the descriptor
rings are set up. The programming of the software style
P R E L I M I N A R Y
Am79C970A
(SWSTYLE, BCR20, bits 7–0) affects the way the de-
scriptor rings and their entries are arranged.
When SWSTYLE is at its default value of ZERO, the de-
scriptor rings are backwards compatible with the
Am79C90 C-LANCE and Am79C96x PCnet-ISA family.
The descriptor ring base addresses must be aligned to
an 8-byte boundary and a maximum of 128 ring entries
is allowed when the ring length is set through the TLEN
and RLEN fields of the initialization block. Each ring
entry contains a subset of the three 32-bit transmit or re-
ceive message descriptors (TMD, RMD) that are organ-
ized as four 16-bit structures (SSIZE (BCR20, bit 8) is
set to ZERO). Note that even though the PCnet-PCI II
controller treats the descriptor entries as 16-bit struc-
tures, it will always perform 32-bit bus transfers to ac-
cess the descriptor entries. The value of CSR2, bits
15–8 is used as the upper 8-bits for all memory ad-
dresses during bus master transfers.
When SWSTYLE is set to ONE, TWO or THREE, the
descriptor ring base addresses must be aligned to a
16-byte boundary and a maximum of 512 ring entries is
allowed when the ring length is set through the TLEN
and RLEN fields of the initialization block. Each ring en-
try is organized as three 32-bit message descriptors
(SSIZE32 (BCR20, bit 8) is set to ONE). The fourth
DWord is reserved. When SWSTYLE is set to THREE,
the order of the message descriptors is optimized to al-
low read and write access in burst mode.
For any software style, the ring lengths can be set be-
yond this range (up to 65535) by writing the transmit and
receive ring length registers (CSR76, CSR78) directly.
Each ring entry contains the following information:
To permit the queuing and de-queuing of message buff-
ers, ownership of each buffer is allocated to either the
PCnet-PCI II controller or the host. The OWN bit within
the descriptor status information, either TMD or RMD, is
used for this purpose. When OWN is set to ONE, it signi-
fies that the PCnet-PCI II controller currently has owner-
ship of this ring descriptor and its associated buffer.
Only the owner is permitted to relinquish ownership or to
write to any field in the descriptor entry. A device that is
not the current owner of a descriptor entry cannot as-
sume ownership or change any field in the entry. A
device may, however, read from a descriptor that it does
not currently own. Software should always read descrip-
tor entries in sequential order. When software finds that
the current descriptor is owned by the PCnet-PCI II
The address of the actual message data buffer in
user or host memory
The length of the message buffer
Status information indicating the condition of the
buffer
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