AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 83

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

levels and skew for Cheapernet, Ethernet and
IEEE-802.3.
Transmitter Timing and Operation
A 20 MHz fundamental mode crystal oscillator provides
the basic timing reference for the MENDEC portion of
the PCnet-PCI II controller. The crystal frequency is
divided by two to create the internal transmit clock refer-
ence. Both the 10 MHz and 20 MHz clocks are fed into
the Manchester Encoder. The internal transmit clock is
used by the MENDEC to synchronize the Internal Trans-
mit Data (ITXDAT) and Internal Transmit Enable
(ITXEN) from the controller. The internal transmit clock
is also used as a stable bit rate clock by the receive sec-
tion of the MENDEC and controller.
The oscillator requires an external 0.01% timing refer-
ence. If an external crystal is used, the accuracy require-
ments are tighter because allowance for the on-board
parasitics must be made to deliver a final accuracy
of 0.01%.
Transmission is enabled by the controller. As long as the
ITXEN request remains active, the serial output of the
controller will be Manchester encoded and appear at
DO . When the internal request is dropped by the con-
Input Signal Conditioning
Transient noise pulses at the input data stream are re-
jected by the Noise Rejection Filter. Pulse width rejec-
tion is proportional to transmit data rate.
The Carrier Detection circuitry detects the presence of
an incoming data frame by discerning and rejecting
noise from expected Manchester data, and controls the
stop and start of the phase-lock loop during clock acqui-
sition. Clock acquisition requires a valid Manchester bit
pattern of 1010b to lock onto the incoming message.
DI
*Internal signal
Receiver
Reject
Noise
Filter
Data
Figure 36. Receiver Block Diagram
P R E L I M I N A R Y
Am79C970A
troller, the differential transmit outputs go to one of two
idle states, dependent on TSEL in the Mode Register
(CSR15, bit 9):
Receiver Path
The principal functions of the receiver are to signal the
PCnet-PCI II controller that there is information on the
receive pair, and separate the incoming Manchester en-
coded data stream into clock and NRZ data.
The receiver section (see the figure below) consists of
two parallel paths. The receive data path is a ZERO
threshold, wide bandwidth line receiver. The carrier path
is an offset threshold bandpass detecting line receiver.
Both receivers share common bias networks to allow
operation over a wide input common mode range.
When input amplitude and pulse width conditions are
met at DI , the internal enable signal from the MENDEC
to controller (IRXEN) is asserted and a clock acquisition
cycle is initiated.
Clock Acquisition
When there is no activity at DI (receiver is idle), the re-
ceive oscillator is phase locked to the internal transmit
clock. The first negative clock transition (bit cell center of
first valid Manchester ZERO) after IRXEN is asserted
TSEL LOW:
TSEL HIGH:
Manchester
The idle state of DO yields ZERO
differential to operate transformer-
coupled loads.
In this idle state, DO+ is positive with
respect to DO– (logical HIGH).
Decoder
Table 9. TSEL Effect
Carrier
Detect
Circuit
AMD
IRXDAT*
IRXCLK*
IRXEN*
19436A-39
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