AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 125

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

8–7PORTSEL[1:0]
LOOP
0
1
1
1
TSEL
When LRT is cleared to ZERO,
the unsquelch threshold for the
RXD circuit will be the standard
10BASE-T value of 300 mV–
520 mV peak.
In either case, the RXD circuit
post
be one half of the unsquelch
threshold.
This bit only has meaning when
the 10BASE-T network interface
is selected.
Read/Write
when either the STOP or the
SPND bit is set. Cleared by
H_RESET or S_RESET and is
unaffected
STOP bit.
Transmit Mode Select. TSEL
controls the levels at which the
AUI drivers rest when the AUI
transmit port is idle. When TSEL
is cleared to ZERO, DO+ and
DO– yield zero differential to op-
erate transformer coupled loads
(Ethernet 2 and 802.3). When
TSEL is set to ONE, the DO+
idles at a higher value with re-
spect to DO–, yielding a logical
HIGH state (Ethernet 1).
This bit only has meaning when
the
is selected.
Read/Write
when either the STOP or the
SPND bit is set. Cleared by
H_RESET or S_RESET.
Port Select bits allow for software
controlled selection of the net-
work medium.
GPSIEN (CSR124, bit 4) must be
set to ONE in addition to pro-
gramming the PORTSEL bits in
order to select the GPSI port as
the active network port.
INTL
X
0
1
1
AUI
squelch
network
by
accessible
accessible
Table 24. Loopback Configuration
threshold
MENDECL
setting
X
X
0
1
interface
P R E L I M I N A R Y
only
only
Am79C970A
the
will
Loopback Mode
Non-loopback
External Loopback
Internal Loopback Include MENDEC
Internal Loopback Exclude MENDEC
6
5
4
FCOLL
DRTY
INTL
PORTSEL settings of AUI and
10BASE-T are ignored when the
ASEL bit of BCR2 (bit 1) has
been set to ONE.
Read/Write
when either the STOP or the
SPND bit is set. Cleared by
H_RESET or S_RESET and is
unaffected
STOP bit.
Internal Loopback. See the de-
scription of LOOP (CSR15, bit 2).
Read/Write
when either the STOP or the
SPND bit is set.
Disable Retry. When DRTY is
set to ONE, PCnet-PCI II control-
ler
transmission. In this mode, the
device will not protect the first 64
bytes of frame data in the trans-
mit FIFO from being overwritten,
because automatic re-transmis-
sion will not be necessary. When
DRTY is cleared to ZERO, the
PCnet-PCI II controller will at-
tempt 16 transmissions before
signaling a retry error.
Read/Write
when either the STOP or the
SPND bit is set.
Force Collision. This bit allows
the collision logic to be tested.
The PCnet-PCI II controller must
be in internal loopback for
FCOLL to be valid. If FCOLL is
set to ONE, a collision will be
forced during loopback transmis-
sion attempts, which will result in
a Retry Error. If FCOLL is cleared
to ZERO, the Force Collision
logic will be disabled. FCOLL is
defined after the initialization
block is read.
will
attempt
by
accessible
accessible
accessible
setting
only
AMD
only
only
only
125
one
the