AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 102

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

terminate all network activity in an orderly sequence be-
fore issuing an S_RESET.
STOP
A STOP reset is generated by the assertion of the STOP
bit in CSR0. Writing a ONE to the STOP bit of CSR0,
when the stop bit currently has a value of ZERO, will in-
itiate a STOP reset. If the STOP bit is already a ONE,
then writing a ONE to the STOP bit will not generate a
STOP reset.
STOP will reset all or some portions of CSR0, 3, and 4 to
default values. For the identity of individual CSRs and bit
locations that are affected by STOP, see the individual
CSR register descriptions. STOP will not affect any of
the BCR and PCI configuration space locations. STOP
will cause the microcode program to jump to its reset
state. Following the end of the STOP operation, the
PCnet-PCI II controller will not attempt to read the
EEPROM device. Setting the STOP bit does not affect
the T-MAU.
Note that STOP will not cause a deassertion of the REQ
signal, if it happens to be active at the time of the
write to CSR0. The PCnet-PCI II controller will wait
until it gains bus ownership and it will first finish all
scheduled bus master accesses before the STOP reset
is executed.
102
31
AMD
Base-Class
MAX_LAT
Reserved
Device ID
24 23
Status
Table 18. PCI Configuration Space Layout
Header Type
Sub-Class
MIN_GNT
Memory Mapped I/O Base Address
Expansion ROM Base Address
P R E L I M I N A R Y
I/O Base Address
Am79C970A
16 15
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Reserved
Programming IF
Latency Timer
STOP terminates all network activity abruptly. The host
can use the suspend mode (SPND, CSR5, bit 0) to ter-
minate all network activity in an orderly sequence before
setting the STOP bit.
Software Access
PCI Configuration Registers
The PCnet-PCI II controller implements a 256-byte con-
figuration space as defined by the PCI specification
revision 2.0. The 64-byte header includes all registers
required to identify the PCnet-PCI II controller and its
function. Additional registers are used to setup the con-
figuration of the PCnet-PCI II controller in a system.
None of the device specific registers located at offsets
40h through FCh are implemented. The layout of the
PCnet-PCI II controller PCI configuration space is
shown in the table below.
The PCI configuration registers are accessible only by
configuration cycles. All multi-byte numeric fields follow
little endian byte ordering. All write accesses to Re-
served locations have no effect; reads from these loca-
tions will return a data value of ZERO.
Interrupt Pin
Command
Vendor ID
8 7
Interrupt Line
Revision ID
Reserved
0
Offset
0Ch
1Ch
2Ch
3Ch
FCh
00h
04h
08h
10h
14h
18h
20h
24h
28h
30h
34h
38h
40h
.
.