AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 157

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

0
BCR20: Software Style
Bit
31–16 RES
15–11 RES
10
RST Pin
APERREN
EDI/EDO
High
Low
Low
Low
Name
Auto Read in
Read accessible always. Write
accessible only when either the
STOP or the SPND bit is set.
ESK is set to ONE by H_RESET
and is not affected by S_RESET
or by setting the STOP bit.
EEPROM
Data Out. Data that is written to
this bit will appear on the EEDI
output of the Microwire interface,
except when the PREAD bit is set
to ONE or the EEN bit is cleared
to ZERO. Data that is read from
this bit reflects the value of
the
Microwire interface.
EDI/EDO has no effect on the
EEDI pin unless the PREAD bit is
cleared to ZERO and the EEN bit
is set to ONE.
Read accessible always. Write
accessible only when either the
STOP or the SPND bit is set.
EDI/EDO is cleared to ZERO by
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
Description
This register is an alias of the lo-
cation CSR58. Accesses to/from
this register are equivalent to ac-
cesses to CSR58.
Reserved locations. Written as
ZEROs and read as undefined.
Reserved locations. Written as
ZEROs and read as undefined.
Advanced Parity Error Handling
Enable. When APERREN is set
to ONE, the BPE bits (RMD1 and
TMD1, bit 23) are used to indi-
cated
transfers to the receive and
transmit buffers. Note that since
the
PREAD or
Progress
X
1
0
0
advanced
EEDO
parity
Table 34. Microwire Interface Pin Assignment
Data
input
error
parity
In/EEPROM
EEN
in
P R E L I M I N A R Y
of
X
X
1
0
error
data
Am79C970A
the
9
8
BCR19[2]
EECS
Active
Low
Low
CSRPCNET
SSIZE32
BCR19[1]
Tri-State
handling uses an additional bit in
the descriptor, SWSTYLE (bits
7–0 of this register) must be set
to ONE, TWO or THREE to pro-
gram the PCnet-PCI II controller
to use 32-bitsoftware structures.
APERREN does not affect the re-
porting of address parity errors or
data parity errors that occur
when the PCnet-PCI II controller
is the target of the transfer.
Read accessible always, write
accessible only when either the
STOP or the SPND bit is set.
APERREN
H_RESET and is not affected by
S_RESET or by setting the
STOP bit.
CSR PCnet-ISA configuration.
When set, this bit indicates that
the PCnet-PCI II controller regis-
ter bits of CSR4 and CSR3 will
map directly to the CSR4 and
CSR3 bits of the PCnet-ISA
(Am79C960)
cleared, this bit indicates that
PCnet-PCI II controller register
bits of CSR4 and CSR3 will map
directly
CSR3
(Am79C900) device.
The value of CSRPCNET is
determined by the PCnet-PCI II
controller
setting of the Software Style
(SWSTYLE,
this register).
Read
CSRPCNET is read only. Write
operations
CSRPCNET will be set after
H_RESET (since SWSTYLE de-
faults to ZERO) and is not
affected by S_RESET or by set-
ting the STOP bit.
32-Bit Software Size. When set,
this
EESK
Active
LED1
bit
bits
to
accessible
indicates
according
will
the
is
of
bits
device.
BCR19[0]
Tri-State
be
LNKST
cleared
Active
the
CSR4
EEDI
AMD
that
7–0
ignored.
to
always.
ILACC
When
157
and
the
the
by
of