AM79C970A Advanced Micro Devices, AM79C970A Datasheet - Page 127

• Manufacturer Part Number: AM79C970A
• Description: PCnet-PCI II Single-Chip Full-Duplex Ethernet Controller for PCI Local Bus Product
• Manufacturer: Advanced Micro Devices

15–0 CRBAU
CSR20: Current Transmit Buffer Address Lower
Bit
31–16 RES
15–0 CXBAL
CSR21: Current Transmit Buffer Address Upper
Bit
31–16 RES
15–0 CXBAU
CSR22: Next Receive Buffer Address Lower
Bit
31–16 RES
15–0 NRBAL
Name
Name
Name
Contains the upper 16 bits of the
current receive buffer address at
which the PCnet-PCI II controller
will store incoming frame data.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
current transmit buffer address
from which the PCnet-PCI II con-
troller is transmitting.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
current transmit buffer address
from which the PCnet-PCI II con-
troller is transmitting.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
next receive buffer address to
which the PCnet-PCI II controller
will store incoming frame data.
accessible
accessible
accessible
P R E L I M I N A R Y
only
only
only
Am79C970A
CSR23: Next Receive Buffer Address Upper
Bit
31–16 RES
15–0 NRBAU
CSR24: Base Address of Receive Descriptor
Ring Lower
Bit
31–16 RES
15–0 BADRL
CSR25: Base Address of Receive Descriptor
Ring Upper
Bit
31–16 RES
15–0 BADRU
Name
Name
Name
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
next receive buffer address to
which the PCnet-PCI II controller
will store incoming frame data.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the lower 16 bits of the
base address of the receive
descriptor ring.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET or by setting the
STOP bit.
Description
Reserved locations. Written as
ZEROs and read as undefined.
Contains the upper 16 bits of the
base address of the receive
descriptor ring.
Read/Write
when either the STOP or the
SPND bit is set. These bits
are unaffected by H_RESET,
accessible
accessible
accessible
accessible
AMD
only
only
only
only
127